• Journal of Power Electronics
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• v.19 no.6
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• pp.1366-1379
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• 2019

High-gain DC/DC converters have become one of the key technologies for the grid-connected operation of new energy power generation, and its research provides a significant impetus for the rapid development of new energy power generation. Inspired by the transformer effect and the ripple-suppressed ability of a coupled inductor, a double-coupled inductor high gain DC/DC converter with a ripple absorption circuit is proposed in this paper. By integrating the diode-capacitor voltage multiplying unit into the quadratic Boost converter and assembling the independent inductor into the magnetic core of structure coupled inductors, the adjustable range of the voltage gain can be effectively extended and the limit on duty ratio can be avoided. In addition, the volume of the magnetic element can be reduced. Very small ripples of input current can be obtained by the ripple absorption circuit, which is composed of an auxiliary inductor and a capacitor. The leakage inductance loss can be recovered to the load in a switching period, and the switching-off voltage spikes caused by leakage inductance can be suppressed by absorption in the diode-capacitor voltage multiplying unit. On the basis of the theoretical analysis, the feasibility of the proposed converter is verified by test results obtained by simulations and an experimental prototype.

• Journal of Power Electronics
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• v.19 no.4
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• pp.881-893
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• 2019

This paper proposes a practical sliding-mode controller design for shaping the impedances of cascaded boost-converter power decoupling circuits for reducing the second order harmonic ripple in photovoltaic (PV) current. The cascaded double-boost converter, when used as power decoupling circuit, has some advantages in terms of a high step-up voltage-ratio, a small number of switches and a better efficiency when compared to conventional topologies. From these features, it can be seen that this topology is suitable for residential (PV) rooftop systems. However, a robust controller design capable of rejecting double frequency inverter ripple from passing to the (PV) source is a challenge. The design constraints are related to the principle of the impedance-shaping technique to maximize the output impedance of the input-side boost converter, to block the double frequency PV current ripple component, and to prevent it from passing to the source without degrading the system dynamic responses. The design has a small recovery time in the presence of transients with a low overshoot or undershoot. Moreover, the proposed controller ensures that the ripple component swings freely within a voltage-gap between the (PV) and the DC-link voltages by the small capacitance of the auxiliary DC-link for electrolytic-capacitor elimination. The second boost controls the main DC-link voltage tightly within a satisfactory ripple range. The inverter controller performs maximum power point tracking (MPPT) for the input voltage source using ripple correlation control (RCC). The robustness of the proposed control was verified by varying system parameters under different load conditions. Finally, the proposed controller was verified by simulation and experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.369-372
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• 2017

This paper presents a control scheme for three-level NPC inverters using small DC-link capacitors. To reduce the inverter system volume, the film capacitor with small capacitance is a promising candidate for the DC-link. When small capacitors are applied in a three level inverter, however, the AC ripple component increases in the DC-link NPV (neutral point voltage). In addition, the three-phase input grid currents are distorted when the DC-link capacitors are fed by diode rectifier. In this paper, the additional circuit is applied to compensate for small capacitor systems defect, and the offset voltage injection method is presented for the stabilization in NPV. These two proposed processes evidently ensure the quality improvement of the input grid currents and output load currents. The feasibility of the proposed method is verified by experimental results.

• Journal of Power Electronics
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• v.18 no.4
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• pp.955-964
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• 2018

In this paper, an active capacitor-diode-switch (CDS) snubber is proposed for L-type current-fed isolated DC-DC converters. The proposed CDS-clamped converter has a number of advantages. It can achieve wide range zero-voltage switching (ZVS) on two switches, a continuous input current with a low ripple, a reduction of one active switch and high efficiency. The operating principles, analysis and parameter design guideline are presented. A 300 W prototype is built to test the proposed converter. Simulation and experimental results are shown at 30 V input voltage and 400 V output voltage.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Journal of Power Electronics
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• v.13 no.4
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• pp.636-646
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• 2013

A single-phase tapped-inductor boost converter has been proposed previously. However, detailed characterization and performance analysis were not conducted. This paper presents a detailed characterization, performance analysis, and design expressions of a single-phase tapped-coupled-inductor boost converter. Expressions are derived for average and RMS input current as well as for RMS input and output capacitor current ripple. A systematic approach for sizing the tapped-coupled inductor, active switch, and output diode is presented; such approach has not been reported in related literature. This study reveals that sizing of the inductor has to be based on current ripple requirement, turns ratio, and load. Conditions that produce discontinuous inductor current are also discussed. Analysis of a non-ideal converter operating in continuous conduction mode is also conducted. The expression for the voltage ratio considering the coupling coefficient is derived. The suitability of the converter for high-voltage step-up applications is evaluated. Factors that affect the voltage boost ratio are also identified. The effects of duty ratio and load variation on the performance of the converter are also investigated. The theoretically derived characteristics are validated through simulations. Experimental results obtained at a low power level are included to validate the analytical and simulation results. A good agreement is observed among the analytical, simulation, and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.3
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• pp.266-273
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• 2012

In this paper, the new open fault detection and tolerant operation method for 3 phase PWM rectifier is proposed. When open fault occurred on the inverter switches of 3 Phase PWM rectifier, the DC link voltage ripple is increased because the input current of the faulty phase is distorted. In this case, the quality of electric power would decrease, and the life time of DC link capacitor is decreased. The open fault is detected by a simple MRAS(Model Reference Adaptive System) without additional hardware sensors, and the tolerant operation carried out by turning on the opposite switch of the faulty switch without any redundancy. By the proposed method, the faulty phase input current can be controlled, so that 3-phase input current is balanced relatively under the faulty condition and the voltage ripple of DC link output is reduced. The validity of the proposed technique is proved on the 6kW 3-phase PWM rectifier system by simulation and experiment.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.189-190
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• 2015

This paper investigates an economic and highly efficient power converter topology and its modulation scheme for 60kW rapid EV charger system. The target system consists of three-phase three-switch buck-type rectifier topology. A new Carrier Based PWM scheme along with its simple implementation using logic gates is introduced in this paper. This PWM scheme replaces the diode rectifier equivalent switching state with an active switching state producing the effectively same current flowing path. As a result, the distortion of input current during the polarity reversal of capacitor line voltage can be mitigated. The proposed modulation technique is confirmed through simulation verification. The proposed modulation technique and its implementation scheme can expand the operation range of the three-phase three-switch buck-type rectifier having ac input and capacitor ripple current of high quality.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.708-712
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• 2001

A new phase-shifted parallel-input/series-output (PI SO) dual inductor-fed push-pull converter for high-power step­up applications is proposed. This converter is operated at a constant duty cycle and employs an auxiliary circuit to control the output voltage with a phase-shift between the two modules. It features a voltage conversion characteristic which is linear to changes in the control input, and high step-up ratio with a greatly reduced switch turn-off stress resulting in a significant increase in the converter efficiency. It also shows a low ripple content and low root-mean-square (RMS) current in the output capacitor. The operational principle is analyzed and a comparative analysis with the conventional pulse-width-modulated (PWM) PISO dual inductor-fed push-pull converter is presented. A 50kHz, 800W, 350Vdc prototype with an input of 20-32Vdc has also been constructed to validate the proposed converter. The proposed converter compares favorably with the conventional counterpart and is considered well suited to high-power step-up applications.