• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.967-973
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• 2009

In this paper, X-band satellite communication oscillator of double phase locked is implemented by constructing a couple of phased-locked loop, and then we have analyzed the phase noise of designed PLL-DRO. The designed phase-locked oscillator is consist of series feedback DRO, frequency divider, phase detector, loop filter and programmable PLL-IC. By dividing oscillation frequency of 12.6 GHz into two frequencies, it exhibits output power of 15.32 dBm at 6.3 GHz. Phase noises of implemented oscillator are -81 dBc/Hz@100Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz and -140.49 dBc/Hz@1 MHz respectively. These indicate excellent stable operation of oscillator and very good phase noise characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.51-59
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• 2009

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13-${\mu}m$ 1-Poly 8-metal CMOS technology, with a core area of $0.58\;mm^2$. Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating $290{\mu}W$ from a 3.3-V supply.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.7
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• pp.282-292
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• 2003

In this paper, we evaluate the performance of WCDMA reverse link receiver system with closed loop fast transmit power control (TPC). For fast power control, SIR must be measured precisely. We propose a new SIR measurement algorithm having a simple structure. The proposed algorithm uses unused OVSF code for interference power evaluation. The proposed SIR measurement algorithm is compared to the conventional SIR measurement algorithm in Ref.$^{［1］}$ under closed loop fast TPC. We adopted WMSA channel estimation filter with Κ=2 for mobile radio channel estimation and considered one slot TPC delay. Extensive computer simulation results show that the proposed algorithm using unused OVSF code reduces the required Ε$_{b}$ /Ι$_{0}$ at the BER of 10$^{-3}$ up to 0.9㏈ and has an improved TPC error performance compared to the conventional algorithm.

• Journal of IKEEE
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• v.16 no.4
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• pp.322-327
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• 2012

In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of $0.096mm^2$.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.742-755
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• 2012

In this paper, we propose a parallel deblocking algorithm to resolve workload imbalance when the deblocking filter of high efficiency video coding (HEVC) decoder is parallelized. In HEVC, the deblocking filter which is one of the in-loop filters conducts two-step filtering on vertical edges first and horizontal edges later. The deblocking filtering can be conducted with high-speed through data-level parallelism because there is no dependency between adjacent edges for deblocking filtering processes. However, workloads would be imbalanced among regions even though the same amount of data for each region is allocated, which causes performance loss of decoder parallelization. In this paper, we solve the problem for workload imbalance by predicting the complexity of deblocking filtering with coding unit (CU) depth information at a coding tree block (CTB) and by allocating the same amount of workload to each core. Experimental results show that the proposed method achieves average time saving (ATS) by 64.3%, compared to single core-based deblocking filtering and also achieves ATS by 6.7% on average and 13.5% on maximum, compared to the conventional uniform data-level parallelism.

• Journal of Power Electronics
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• v.16 no.1
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• pp.297-309
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• 2016

Grid-connected inverters (GCIs) with an LCL output filter have the ability of attenuating high-frequency (HF) switching ripples. However, by using only grid-current control, the system is prone to resonances if it is not properly damped, and the current distortion is amplified significantly under highly distorted grid conditions. This paper proposes a synchronous reference frame equivalent proportional-integral (SRF-EPI) controller in the αβ stationary frame using the parallel virtual resistance-based active damping (PVR-AD) strategy for grid-interfaced distributed generation (DG) systems to suppress LCL resonance. Although both a proportional-resonant (PR) controller in the αβ stationary frame and a PI controller in the dq synchronous frame achieve zero steady-state error, the amplitude- and phase-frequency characteristics differ greatly from each other except for the reference tracking at the fundamental frequency. Therefore, an accurate SRF-EPI controller in the αβ stationary frame is established to achieve precise tracking accuracy. Moreover, the robustness, the harmonic rejection capability, and the influence of the control delay are investigated by the Nyquist stability criterion when the PVR-based AD method is adopted. Furthermore, grid voltage feed-forward and multiple PR controllers are integrated into the current loop to mitigate the current distortion introduced by the grid background distortion. In addition, the parameters design guidelines are presented to show the effectiveness of the proposed strategy. Finally, simulation and experimental results are provided to validate the feasibility of the proposed control approach.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1272-1280
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• 2008

In this paper, we have proposed a phase noise model of fast frequency hopping synthesizer with DDS Driven PLL architecture. To accurately model the phase noise contribution of noise sources in frequency hopping synthesizer, they were investigated using model of digital divider for PLL, DAC for DDS and Leeson's model for reference oscillator and VCO. Especially it was proposed that the noise component of low pass filter was considered together with the phase noise of VCO. Under assuming linear operation of a phase locked loop, the phase noise transfer functions from noise sources to the output of synthesizer was analyzed by superposition theory. The proposed phase noise prediction model was evaluated and its results were compared with measured data.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.8
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• pp.14-25
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• 2002

In this paper, we propose a modified AFC algorithm which is suitable for the implementation of WCDMA reverse link receiver modem. To reduce the complexity, the modified CP-FDD algorithm named 'Normalized CP-FDD' is applied to the AFC loop. The proposed FDD algorithm overcomes the conventional CP-FDD's sensitivity to the variance of input signal amplitude and increases the linear range of S -curve. Therefore, offset frequency estimation using the proposed scheme can be more stable than the conventional method. Unlike IS-95, since pilot symbol in WCDMA is not transmitted continuously, we introduce a moving average filter at the FDD input to increase the number of cross-product. So, tracking speed and stability are improved. For more rapid frequency acquisition and tracking, we adopt a multi-stage tracking mode. Using NCO having ROM table structure, the frequency offset is compensated. We applied the proposed algorithm in the implementation of WCDMA base station modem successfully.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.168-180
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• 2018

In order to achieve the high quality output voltage of single-phase voltage source inverters, in this paper an Adaptive Complementary Sliding Mode Control (ACSMC) is proposed. Firstly, the dynamics model of the single-phase inverter with lumped uncertainty including parameter variations and external disturbances is derived. Then, the conventional Sliding Mode Control (SMC) and Complementary Sliding Mode Control (CSMC) are introduced separately. However, when system parameters vary or external disturbance occurs, the controlling performance such as tracking error, response speed et al. always could not satisfy the requirements based on the SMC and CSMC methods. Consequently, an ACSMC is developed. The ACSMC is composed of a CSMC term, a compensating control term and a filter parameters estimator. The compensating control term is applied to compensate for the system uncertainties, the filter parameters estimator is used for on-line LC parameter estimation by the proposed adaptive law. The adaptive law is derived using the Lyapunov theorem to guarantee the closed-loop stability. In order to decrease the control system cost, an inductor current estimator is developed. Finally, the effectiveness of the proposed controller is validated through Matlab/Simulink and experiments on a prototype single-phase inverter test bed with a TMS320LF28335 DSP. The simulation and experimental results show that compared to the conventional SMC and CSMC, the proposed ACSMC control strategy achieves more excellent performance such as fast transient response, small steady-state error, and low total harmonic distortion no matter under load step change, nonlinear load with inductor parameter variation or external disturbance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.100-105
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• 2010

In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.