• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.333-336
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• 2000

Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.5
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• pp.623-629
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• 2018

The acceleration and the angular velocity that include natural frequencies of a missile detected by Inertial Measurement Unit(IMU) are transmitted to the control loop of a missile. The control loop command that is calculated using above signals can cause the resonance of the missile while it flies. Hence it is common to adapt the filter and the control loop for attenuating or eliminating the undesired signals such as natural frequencies. This paper introduces the new test technique using a floating system for performance evaluation of the designed filter and the control loop prior to a flight test. The proposed scheme can check out the degradation property of vibration in the filter and the control loop, while the conventional hardware-in-the-loop simulation(HILS) scheme cannot.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.2
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• pp.123-128
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• 2020

A low phase noise phase locked loop (PLL) with negative feedback loop including frequency variation sensing circuit (FVSC) has been proposed. The FVSC senses the frequency variation of voltage controlled oscillator output signal and controls the volume of electric charge in loop filter capacitance. As the output frequency of the phase locked loop increases, the FVSC reduces the loop filter capacitor charge. This causes the loop filter output voltage to decrease, resulting in a phase locked loop output frequency decrease. The added negative feedback loop improves the phase noise characteristics of the proposed phase locked loop. The size of capacitance used in FVSC is much smaller than that of loop filter capacitance resulting in no effect in the size of the proposed PLL. The proposed low phase noise PLL with FVSC is designed with a supply voltage of 1.8V in a 0.18㎛ CMOS process. Simulation results show the jitter of 273fs and the locking time of 1.5㎲.

• Journal of electromagnetic engineering and science
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• v.17 no.2
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• pp.86-90
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• 2017

In this study, a novel third-order bandpass filter, which is based on a rectangular closed loop resonator, is presented. By adding a series resonator to the conventional loop resonator, the resonator's even resonant mode is split into two modes, while the odd resonant mode is not affected. Therefore, by varying the values of the series resonator elements, the resonant frequencies of two even modes can be determined independent of the odd-mode resonant frequency. In the proposed triple-mode filter design, instead of using a lumped series resonator, a T-shaped transmission line is coupled to the resonator via a small gap. To verify the design method, a filter is designed at 2.4 GHz with a bandwidth of 100 MHz. The improved performances of the proposed triple-mode filter are compared with those of the conventional dual mode filter.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.233-236
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• 2005

Phase noise in a phase-locked-loop (PLL) is unwanted and unavoidable. It is a main concern in oscillation system especially PLL. The phase noise is derived in term of power spectrum density by using a reliable phase noise model. There are four noise sources being considered in this paper, which are generated by reference oscillator, voltage controlled oscillator, filter, and main divider. The major concern for this paper is the noise from the filter. Two types of second order low pass filter are used in the PLL system. Applying the mathematical phase noise model, the output noises are compared. The total noise from the passive filter is lower than the active filter at the offset frequency range between 1 Hz to 33 kHz.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1506-1509
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• 2013

본 논문에서는 고성능 HEVC(High Efficiency Video Coding) 복호기 설계를 위한 효율적인 in-loop filter의 하드웨어 구조 설계에 대해 기술한다. in-loop filter는 deblocking filter와 SAO로 구성되며, 블록 단위 영상 압축 및 양자화 등에서 발생하는 정보의 손실을 보상하는 기술이다. 하지만 HEVC는 $64{\times}64$ 블록 크기까지 화소 단위 연산을 수행하기 때문에 높은 연산시간 및 연산량이 요구된다. 따라서 본 논문에서 제안하는 in-loop filter의 deblocking filter 모듈과 SAO 모듈은 최소 연산 단위인 $8{\times}8$ 블록 연산기로 구성하여 하드웨어 면적을 최소화하였다. 또한 SAO에서는 $8{\times}8$ 블록의 연산 결과를 내부레지스터에 저장하는 구조로 $64{\times}64$ 블록 크기를 지원하도록 설계하여 연산시간 및 연산량을 최소화 하였다. 제안하는 하드웨어 구조는 Verilog HDL로 설계하였으며, TSMC 칩 공정 180nm 셀 라이브러리로 합성한 결과 동작 주파수는 270MHz이고, 전체 게이트 수는 48.9k이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.479-486
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• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• Journal of Power Electronics
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• v.11 no.4
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• pp.456-463
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• 2011

Grid-connected converters have widely adopted LCL filters to acquire high harmonic suppression. However, the LCL filter increases the system order so that the design of the system stability would be complicated. Recently, sole-loop control strategies have been used for grid-connected converters with L or LC filters. But if the sole-loop control is directly transplanted to grid-connected converters with LCL filters, the systems may be unstable. This paper presents a novel dual-loop power control strategy composed of a power outer loop and a current inner loop. The outer loop regulates the grid-connected power. The inner loop improves the system stability margin and suppresses the resonant peak caused by the LCL filter. To obtain the control variables, a single-phase current detection is proposed based on PQ theory. The system transfer function is derived in detail and the influence of control gains on the system stability is analyzed with the root locus. Simulation and experimental results demonstrate the feasibility of the proposed control.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2495-2502
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• 2012

This paper presents a new structure of phase looked loop (PLL) for replacing a process sensitive resistor in loop filter with an additional charge pump (CP). The additional charge pump works as a resistor in a loop filter. The output of two charge pumps changes same direction according to process variation. The simulation results according to process conditions(SS/TT/FF) demonstrate that the proposed PLL works properly with process variations. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by simulation with HSPICE.