• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.281-284
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• 2002

Rijndael algorithm is known to a new private key block cipher which is substitute for DES. Rijndael algorithm is adequate to both hardware and software implementation, so hardware implementation of Rijndael algorithm is applied to high speed data encryption and decryption. This paper describes three implementation methods of Rijndael S-box, which is important factor in performance of Rijndael coprocessor. It shows synthesis results of each S-box implementation in Xilinx FPGA. Tllc lilree S-box implementation methods are implementation using lookup table only, implementation using both lookup table and combinational logic, and implementation using combinational logic only.

• Journal of Information Processing Systems
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• v.15 no.4
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• pp.890-903
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• 2019

The single carrier frequency domain equalization (SC-FDE) technology is an important part of the broadband wireless access communication system, which can effectively combat the frequency selective fading in the wireless channel. In SC-FDE communication system, the accuracy of timing synchronization directly affects the performance of the SC-FDE system. In this paper, on the basis of Schmidl timing synchronization algorithm a timing synchronization algorithm suitable for FPGA (field programmable gate array) implementation is proposed. In the FPGA implementation of the timing synchronization algorithm, the sliding window accumulation, quantization processing and amplitude reduction techniques are adopted to reduce the complexity in the implementation of FPGA. The simulation results show that the algorithm can effectively realize the timing synchronization function under the condition of reducing computational complexity and hardware overhead.

• ETRI Journal
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• v.31 no.2
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• pp.240-242
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• 2009

A computationally efficient implementation of the progressive edge-growth algorithm is presented. This implementation uses an array of red-black (RB) trees to manage the layered structure of check nodes and adopts a new strategy to expand the Tanner graph. The complexity analysis and the simulation results show that the proposed approach reduces the computational effort effectively. In constructing a low-density parity check code with a length of $10^4$, the RB-tree-array-based implementation takes no more 10% of the time required by the original method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.55-64
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• 2004

In this paper, we propose an efficient FFT algorithm for high speed multimedia communication systems, and present its pipeline implementation results. Since the proposed algorithm is based on the radix-4 butterfly unit, the processing rate can be twice as fast as that based on the radix-2$^3$ algorithm. Also, its implementation is more area-efficient than the implementation from conventional radix-4 algorithm due to reduced number of nontrivial multipliers like using the radix-23 algorithm. In order to compare the proposed algorithm with the conventional radix-4 algorithm, the 64-point MDC pipelined FFT processor based on the proposed algorithm was implemented. After the logic synthesis using 0.6${\mu}{\textrm}{m}$ technology, the logic gate count for the processor with the proposed algorithm is only about 70% of that for the processor with the conventional radix-4 algorithm. Since the proposed algorithm can be achieve higher processing rate and better efficiency than the conventional algorithm, it is very suitable for the high speed multimedia communication systems such as WLAN, DAB, DVB, and ADSL/VDSL systems.

• Korean Management Science Review
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• v.17 no.2
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• pp.1-12
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• 2000

In this study, we deals with the implementation of an optimal basis identification procedure for interior point methods. Our implementation is based on Megiddo’s strongly polynomial algorithm applied to Andersen and Ye’s approximate LP construction. Several techniques are explained such as the use of effective indicator for obtaining optimal partition when constructing the approximate LP, the efficient implementation of the problem reduction technique proposed by Andersen, the crashing procedure needed for fast dual phase of Megiddo’s algorithm and the construction of the stable initial basis. By experimental comparison, we show that our implementation is superior to the crossover scheme implementation.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.9
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• pp.755-760
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• 2005

This paper proposes an improved implementation algorithm for the continuous-time receding horizon control (RHC). The proposed algorithm has a feature that it has better control performance than the existing algorithm. Main idea of the proposed algorithm is that we can approximate the original RHC problem better by assuming the predicted input trajectory on the prediction horizon has a continuous form, which is constructed from linear interpolation of finite number of vectors. This, in turn, leads to improved control performance. We derive a predictor such that it takes linear interpolation into account and proposes the method by which we can express the cost exactly. Through simulation study fur an inverted pendulum, we illustrate that the proposed algorithm has the better control performance than the existing one.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.41-46
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• 2012

In this paper, An efficient circuit design algorithm considering constraint is proposed. The proposed algorithm sets up in time constraint and area constraint, power consumption constraint for a circuit implementation. First, scheduling process for time constraint. Select the FU(Function Unit) which is satisfied with time constraint among the high level synthesis results. Analyze area and power consumption of selected FUs. Constraint set for area and power constraint. Device selection to see to setting condition. Optimization circuit implementation in selected device. The proposed algorithm compared with [7] and [8] algorithm. Therefore the proposed algorithm is proved an efficient algorithm for optimization circuit implementation.

• Journal of KIISE:Information Networking
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• v.31 no.3
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• pp.314-326
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• 2004

Bluetooth has been reputed as a wireless ad-hoc networking technology supplying scalable and extensible networks between digital devices. For that kind of networks, scatternet is a most essential part in bluetooth. But past researches on bluetooth scatternet has proposed only possibilities of scatternet algorithm based on simulation results. And many of the researches failed in guaranteeing extensibility and flexibility and had many difficulties in real hardware implementation. In this paper, we proposed node ring scatternet(NRS) algorithm guaranteeing extensible and flexible networks. NRS algorithm is designed for hardware implementation using real commercial bluetooth module. That algorithm is divided into initial formation and reformation. For initial formation, we proposed limited SEEK/SCAN algorithm. For reformation, we proposed DIAC algorithm and Reserved Recovery Node algorithm. And we proposed SFMP(Scatternet Formation ＆ Management Protocol) in protocol stack for real implementation. NRS algorithm is operated in SFMP. Finally, we performed real hardware experiments and evaluated the proposed algorithm. In that experiments, we succeeded in forming scatternet up to 20 nodes. In comparison with other similar algorithm, proposed algorithm have the improvement in scatternet formation delay and success rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1005-1015
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• 1999

This paper is concerned with an improvement on IFFT (inverse fast Fourier transform) and FFT based baseband digital implementation algorithm for BPSK (binary phase shift keying)-modulated MC-CDMA (multicarrier-code division multiple access) systems, that is functionally equivalent to the conventional implementation algorithm, while reducing computational complexity and bandwidth requirement. We also derive an equalizer structure for the proposed implementation algorithm. The proposed algorithm is based on a variant of FFT algorithm that utilizes a N/2-point FFT/IFFT for simultaneous transformation and reconstruction of two N/2-point real signals. The computer simulations under additive white Gaussian noise channels and frequency selective fading channels using equal gain combiner and maximal ratio combiner diversities, demonstrate the performance of the proposed algorithm.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.855-858
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• 1999

In this paper, we present a FPCA implementation of IDEA algorithm. Target technology is Altera FLEX 10K FPCA. The correctness of the implementation is verified by the timing simulation with max+plus II.