• Journal of KIISE:Computing Practices and Letters
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• v.16 no.6
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• pp.673-677
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• 2010

Recently, NAND flash memory has been widely used in embedded systems, personal computers, and server systems because of its attractive features, such as non-volatility, fast access speed, shock resistance, and low power consumption. Due to its hardware characteristics, specifically its 'erase-before-write' feature, Flash Translation Layer is required for using flash memory like hard disk drive. Many FTL schemes have been proposed, but conventional FTL schemes have problems such as block thrashing and block associativity problem. The KAST scheme tried to solve these problems by limiting the number of associations between data block and log block to K. But it has also block thrashing problem in random access I/O pattern. In this paper, we proposed a new FTL scheme, UDA-LBAST. Like KAST, the proposed scheme also limits the log block association, but does not limit data block association. So we could minimize the cost of merge operations, and reduce merge costs by using a new block reclaim scheme, log block garbage collection.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.1-10
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• 2020

In this paper, we propose an efficient disk buffer replacement policy which improves hit ratio and reduces writing operations of flash based storages. The flash based storage has many advantages, including a small form factor, non-volatility and high reliability, but there are problems caused by own limitations, like not-in-place update, short life cycle and asymmetric I/O latencies. To redeem these problems, this paper proposes the write weighted probability of reference(2WPR) policy. 2WPR policy predicts re-referencing probability and calculates localities of each page. Furthermore, by weighting write operations to every pages, 2WPR can reduce write operations to flash based storage. In addition, we can improve the performance with higher hit ratio and reduce the number of write operations and consequently shorten the latencies of each operation. The results show that our policy provides improvements of up to 10% for the hit ratio with the reduction of up to 5% for the flash writing operation compared with other policies.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.9
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• pp.898-903
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• 2010

Popularity of smartphones such as Google Android phones and Apple iphones, is increasing the demand on more reliable high performance file system for flash memory. In this paper, we propose two techniques to improve the performance of YAFFS (Yet Another Flash File System), while enhancing the reliability of the system. Specifically, we first propose to manage metadata and user data separately on segregated blocks and indexing information piggy-back technique for reducing mount time and also enhancing performance. Second, we tailor the wear-leveling to the segregated metadata and user data blocks. Performance evaluation results based on real hardware system with 1GB NAND flash memory show that the YAFFS with our proposed techniques realized outperforms the original YAFFS by six times in terms of mount speed and five times in terms of benchmark performance, while reducing the average erase count of blocks by 14%.

• Journal of Computing Science and Engineering
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• v.8 no.3
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• pp.157-172
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• 2014

Contemporary embedded systems often use NAND flash memory instead of hard disks as their swap space of virtual memory. Since the read/write characteristics of NAND flash memory are very different from those of hard disks, an efficient page replacement algorithm is needed for this environment. Our analysis shows that temporal locality is dominant in virtual memory references but that is not the case for write references, when the read and write references are monitored separately. Based on this observation, we present a new page replacement algorithm that uses different strategies for read and write operations in predicting the re-reference likelihood of pages. For read operations, only temporal locality is used; but for write operations, both write frequency and temporal locality are used. The algorithm logically partitions the memory space into read and write areas to keep track of their reference patterns precisely, and then dynamically adjusts their size based on their reference patterns and I/O costs. Without requiring any external parameter to tune, the proposed algorithm outperforms CLOCK, CAR, and CFLRU by 20%-66%. It also supports optimized implementations for virtual memory systems.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.96-99
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• 2021

NVRAM(Non-volatile RAM)이란 전원을 공급하지 않아도 데이터를 유지할 수 있는 RAM 이다. 비휘발성 메모리이기 때문에 Flash 와 동일한 기능을 제공할 수 있다. 또한 Flash 에 비해 저전력으로 동작하고, 읽고 쓰는 동작도 더 빠르며 내구성까지 뛰어나다. 즉, NVRAM 은 리소스가 제한적인 사물인터넷(IoT) 장치에서 Flash 를 대신하여 전력소모 및 지연시간 측면에서 효과적으로 사용될 수 있는 메모리이다. IoT 장치는 일반적으로 배터리와 같은 독립전원 장치로 작동하거나, 최근에는 에너지 하베스터를 활용한 간헐적 컴퓨팅 방식도 활용되고 있다. 간헐적 컴퓨팅 방식에서는 전원이 꺼졌을 때도 프로그램의 상태를 유지하기 위해 비휘발성 메모리에 백업동작이 필수적이다. 그러므로 백업을 위한 메모리를 Flash 가 아닌 NVRAM 으로 대체하게 되면 효율적이고, 상대적으로 백업 및 복구에 의한 비휘발성 메모리에 접근이 많은 간헐적 컴퓨팅에서는 더 큰 효율을 볼 수 있다. 하지만 현재 NVRAM 이 내장된 개발보드가 제한적이고, NVRAM 을 외부 모듈로서 사용하기 위해 SPI 또는 I2C 통신을 사용해야 한다. 그 외에도 동시에 공유 메모리에 접근하는 등의 문제를 막아야 한다. 이러한 문제를 막고, NVRAM 을 편리하게 사용할 수 있도록 추상화 계층을 만들어 NVRAM 테스팅 환경을 제공하여 해당 분야의 연구개발을 가속화할 수 있을 것으로 기대된다. 본 논문에서는 NVRAM 의 한 종류인 FRAM 을 사용하여 추상화 계층을 구현하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.45-52
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• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.

• Journal of Energy Engineering
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• v.12 no.3
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• pp.184-189
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• 2003

A study of the property of Indolene-Methanol Plus High Alcolhols (MPHA) has been completed. The study invested the measurement of fuel properties. The fuel properties investigated are distillation characteristics, heating value, flash point, specific gravity and water tolerance. The alcohol concentration was varied from 0 to 100 percent by volume in clear Indolene. The measurement of fuel properties indicated that, in general, Indolene-MPHA blends have higher water tolerance, similar specific gravity, similar flash point and different distillation characteristics compared to Indolene-Methanol blends.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.22 no.1
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• pp.76-84
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• 2014

Heavy Rainfall event accompanying with Mesoscale Convective Systems(MCSs) inducing flash flooding and Kimpo and Inchon International Airport closing over Seoul metropolitan area was investigated this study. This heavy rainfall event was occurred through the synoptic scale boundary of North Pacific Subtropical high, Typhoon and also can predicted by proper analysis of various forecasting parameters such as abundant moisture, instabilities, and synoptic/mesoscale forcing.

• Journal of KIISE:Databases
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• v.34 no.2
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• pp.133-140
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• 2007

Flash memory has penetrated our life in various forms. For example, flash memory is important storage component of ubiquitous computing or mobile products such as cell phone, MP3 player, PDA, and portable storage kits. Behind of the wide acceptance as memory is many advantages of flash memory: for instances, low power consumption, nonvolatile, stability and portability. In addition to mentioned strengths, the recent development of gigabyte range capacity flash memory makes a careful prediction that the flash memory might replace some of storage area dominated by hard disks. In order to have overwriting function, one block must be erased before overwriting is performed. This difference results in the cost of reading, writing and erasing in flash memory[1][5][6]. Since this difference has not been considered in traditional buffer replacement technologies adopted in system software such as OS and DBMS, a new buffer replacement strategy becomes necessary. In this paper, a new buffer replacement strategy, reflecting difference I/O cost and applicable to flash memory, suggest and compares with other buffer replacement strategies using workloads as Zipfian distribution and real data.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.56-62
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• 1999

All the cells on the whole memory array or a block of the memory array in the Flash EEPROM's are erased at the same time using Fowler-Nordheim (FN) tunneling. some of the cels are often overerased since the tunneling is not a self-limited process. In this paper, the optimum doping concentration of the floating gate solve the overerase problem has been studied. For these studies, N-type MOSFETs and MOS capacitors with various doping concentrations of the gate polysilicon have been fabricated and their electrical characteristics have been measured and analyzed. As the results of the experiment, it has been found that the overerase problem can be prevented if the doping concentration of the floating gate is low enough (i.e. below $1.3{\times}10^{18}/cm^3$). It is because the potential difference between the floating gate and the source is lowered due to the formation of the depletion layer in the floating gate and thus the erasing operation stops by itself after most of the electrons stored in the floating gate are extracted. On the other hand, the uniformity of the Vt and the gm has been significantly poor if the coping concentration of the floating, gate is too much lowered (i.e. below $1.3{\times}10^{17}/cm^3$), which is believed to be due to nonuniform loss of the dopants from the nonuniform segregation in the floating gate. Consequently, the optimum doping concentration of the floating gate to suppress the overerase problem and get the uniform Vt and has been found to range from $1.3{\times}10^{17}/cm^3$ to $1.3{\times}10^{18}/cm^3$ in the Flash EEPROM.