DOI QR코드

DOI QR Code

2WPR: Disk Buffer Replacement Algorithm Based on the Probability of Reference to Reduce the Number of Writes in Flash Memory

  • Lee, Won Ho (Dept. of Computer Engineering, Yeungnam University) ;
  • Kwak, Jong Wook (Dept. of Computer Engineering, Yeungnam University)
  • Received : 2019.12.24
  • Accepted : 2020.01.17
  • Published : 2020.02.28

Abstract

In this paper, we propose an efficient disk buffer replacement policy which improves hit ratio and reduces writing operations of flash based storages. The flash based storage has many advantages, including a small form factor, non-volatility and high reliability, but there are problems caused by own limitations, like not-in-place update, short life cycle and asymmetric I/O latencies. To redeem these problems, this paper proposes the write weighted probability of reference(2WPR) policy. 2WPR policy predicts re-referencing probability and calculates localities of each page. Furthermore, by weighting write operations to every pages, 2WPR can reduce write operations to flash based storage. In addition, we can improve the performance with higher hit ratio and reduce the number of write operations and consequently shorten the latencies of each operation. The results show that our policy provides improvements of up to 10% for the hit ratio with the reduction of up to 5% for the flash writing operation compared with other policies.

본 논문에서는 향상된 히트율과 더 적은 낸드 플래시 메모리 쓰기 연산을 할당하는 디스크 버퍼 교체 정책을 소개한다. 플래시 메모리는 높은 집적도, 높은 신뢰성 및 비휘발성이라는 특징을 가지고 있어 최근 많은 곳에서 사용되고 있다. 하지만 삭제 이후 쓰기 연산 문제, 비대칭적인 연산 속도와 짧은 수명 등의 한계점도 가지고 있다. 이런 문제를 개선하기 위해 본 논문에서는 2WPR 정책을 소개한다. 2WPR 정책은 디스크 버퍼의 각 페이지마다 이후 재참조될 가능성, 각 지역성 및 쓰기 연산에 대한 가중치 분석을 통해 교체할 페이지를 선택한다. 제안된 새로운 정책은 기존 디스크 버퍼 관리 정책에 비해 히트율을 최대 10%까지 향상시킬 수 있으며 플래시 메모리에 대한 쓰기 연산을 최대 5%까지 감소시킬 수 있었다.

Keywords

References

  1. R. Caceres, F. Douglis, Kai Li and B. Marsh, "Operating system implications of solid-state mobile computers", Proceedings of IEEE 4th Workshop on Workstation Operating Systems. WWOS-III, pp. 21-27, October 1993.
  2. Lawton, George, "Improved flash memory grows in popularity", Computer, Vol. 39, No. 1, pp. 16-18, 2006. https://doi.org/10.1109/MC.2006.22
  3. Kim, Han-joon, and Sang-goo Lee, "A new flash memory management for flash storage system", Proceedings. Twenty-Third Annual International Computer Software and Applications Conference (Cat. No. 99CB37032), pp 248-289, 1999.
  4. Dong, Xiangyu and Xu, Cong and Xie, Yuan and Jouppi, Norman P, "Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 7, pp. 994-1007, 2012. https://doi.org/10.1109/TCAD.2012.2185930
  5. Saxena, Mohit and Swift, Michael M, "FlashVM: Virtual Memory Management on Flash.", USENIX Annual Technical Conference, 2010.
  6. Xie, Yuan, "Emerging Memory Technologies: Design, Architecture, and Applications", pp. 15-50, 2013.
  7. Yang, Ming-Chang and Chang, Yuan-Hao and Tsao, Che-Wei and Huang, Po-Chun, "New ERA: New efficient reliability-aware wear leveling for endurance enhancement of flash storage devices", 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1-6, 2013.
  8. Hong, Seongcheol and Shin, Dongkun, "NAND flash-based disk cache using SLC/MLC combined flash memory", 2010 International Workshop on Storage Network Architecture and Parallel I/Os, pp. 21-30, 2010.
  9. Karmakar, Supriya, "Quantum dot gate non-volatile memory as single level cell (SLC), multi-level cell (MLC) and triple level cell (TLC)", 2018 IEEE Long Island Systems, Applications and Technology Conference (LISAT), pp. 1-5, 2018.
  10. Bennett, Sorcha and Sullivan, Joe, "The Characterisation of TLC NAND Flash Memory, Leading to a Definable Endurance/Retention Trade-Off", International Journal of Computer, Electrical, Automation, Control and Information Engineering, Vol. 10, pp.716-723, 2016.
  11. Panagakis, Antonis and Vaios, Athanasios and Stavrakakis, Ioannis, "Approximate analysis of LRU in the case of short term correlations", Computer Networks, Vol. 52, No. 6, pp. 1142-1152, 2008. https://doi.org/10.1016/j.comnet.2007.12.006
  12. Park, Seon-yeong and Jung, Dawoon and Kang, Jeong-uk and Kim, Jin-soo and Lee, Joonwon, "CFLRU: a replacement algorithm for flash memory", Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, pp. 234-241, 2006.
  13. Nicola, Victor F and Dan, Asit and Dias, Daniel M, "Analysis of the generalized clock buffer replacement scheme for database transaction processing", Vol. 20, No. 1, pp. 35-46, 1992. https://doi.org/10.1145/149439.133084
  14. Cui, Jinhua and Wu, Weiguo and Wang, Yinfeng and Duan, Zhangfeng, "PT-LRU: a probabilistic page replacement algorithm for NAND flash-based consumer electronics", IEEE Transactions on Consumer Electronics, Vol. 60, No. 4, pp. 614-622, 2014. https://doi.org/10.1109/TCE.2014.7027334
  15. Yuan, Youwei and Zhang, Jintao and Han, Guangjie and Jia, Gangyong and Yan, Lamei and Li, Wanqing, "DPW-LRU: An Efficient Buffer Management Policy Based on Dynamic Page Weight for Flash Memory in Cyber-Physical Systems", IEEE Access, Vol. 7, pp. 58810-58821, 2019. https://doi.org/10.1109/access.2019.2914231
  16. Du, Chenjie and Yao, Yingbiao and Zhou, Jie and Xu, Xiaorong, "VBBMS: A Novel Buffer Management Strategy for NAND Flash Storage Devices", IEEE Transactions on Consumer Electronics, Vol. 65, No. 2, pp. 134-141, 2019. https://doi.org/10.1109/tce.2019.2910890