• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.20-23
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• 2008

We proposed a-Si:H TFT (hydrogenated amorphous silicon thin film transistor) level shifter which reduced number of power sources. To reduce the number of power sources from four to two, modified bootstrapped inverter was used for the level shifter. The shift register was verified by PSPICE circuit simulation and fabricated. The fabricated level shifter successfully shifted low input (0 to 5 V) to high level output (-7 to 23 V).

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.711-714
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• 2006

Properties of silicon nitride ($SiN_x$) film including physical and electrical characteristics have been studied for improving the stability of hydrogenated amorphous silicon thin-film transistors (a-Si TFTs) in active-matrix liquid-crystal displays (AMLCDs). The instability of a-Si:H TFTs is estimated by accelerated stress test of both bias-temperature stress and bias-illumination stress. The results show that the deposition conditions of $SiN_x$ films with higher power and lower pressure are the best choice for improving the on-current and stability of TFTs.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.117-124
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• 1996

The .mu.c-Si:H films have been deposited by PeCVD at the various conditions such as hydrogen dilution ratio, substrate temperature and RF power density. Then, we studied their electrical and optical properties. Top gate hydrogenated micro-crystalline silicon thin film transistors($\mu$c-Si:H TFTs) using $\mu$-Si:H and a-SiN:H films have been fabricated by FECVD. The electrical characteristics of the devices have been investigated by semiconductor parameter analyzer and compared with amorphous silicon thin film transistors (a-Si:H TFTs). In this study, on/off current ratio, threshold voltage and the field effect mobility of the $\mu$c-Si:H TFT were $3{\times}10^{4}$, 5.06V and 0.94cm$^{2}$Vs, respectively.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1019-1021
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• 1995

Light induced degradation of hydrogenated amorphous silicon(a-Si:H) are related to the number of weak dangling bonds which are thought to be responsible for the Staebler-Wronski effects, and caused the many photoelectric problems in applications of thin film transistors and solar cell, etc. In this paper, we deposited fluorinated amorphous silicon films(a-Si:H;F) with $SiH_4$ and $SiF_4$ gas mixture and investigated the effects of fluorine atoms on the evoluations of the crystallinity and improvements of light instability. We have found that micro-crystallinity produced in a-SI:H;F films and marked maximum value of 22% at the flow rate of $SiH_4:SiF_4$=2:10 sccm by UV spectrophotometer measurement, while n-Si:H film deposited with only $SiH_4$ gas showed no crystallinity. Light-induced degradation property of a-Si:H;F films is also improved which is mainly due to the etching effects of fluorine atoms on the weak Si-Si bonds and unstable hydrogen bonds. It is considered that involving fluorine atoms in a-Si:H films may contribute to the suppression of light-induced degradation and evolution of micro-crystallinity.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.193-193
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• 2013

실리콘 박막 태양전지는 광 흡수층에서 형성된 정공과 전자를 효과적으로 분리하기 위해 p형과 n형으로 도핑된 층을 형성하는 p-i-n구조를 갖게 된다. 이러한 도핑 층을 형성하기 위해 B2H6와 PH3와 같은 독성 가스를 사용하기 때문에, 공정 안정성과 환경적인 이슈가 대두된다. 또한 도핑은 추가적으로 실리콘 박막 태양전지의 안정화 효율을 지속적으로 저하시키는 요인이 된다. 이러한 문제점을 개선하기 위하여, 창층으로 MoO3, V2O5, WO3 등과 같이 높은 일함수를 갖는 전이금속 산화물을 사용하고, 광 흡수층으로 i-Si:H을, 후면 전극으로 낮은 일함수를 나타내는 LiF/Al을 사용하였다. 전이금속 산화물과 LiF/Al의 큰 일함수 차이에 의해서 흡수층인 i-Si:H 에서 생성된 캐리어들은 효과적으로 분리되고 수집이 된다. 금속 산화물은 스퍼터링 공정에 의하여 이루어졌으며, 스퍼터링 공정조건에 따라 산화도가 조절되며, 이러한 산화도에 따라 태양전지의 셀 특성이 결정된다. 도핑 층이 없는 새로운 형태의 실리콘 박막 태양전지는 기존 비정질 실리콘 박막 태양전지에 비해 높은 안정화 효율을 나타내며, 이는 도핑 층이 없기 때문에 기존 실리콘 박막 태양전지의 열화현상에 따른 효율저하가 발생하지 않는 장점을 지내고 있다.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1295-1296
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• 2006

수소화된 비정질 실리콘 박막 트랜지스터(a-Si:H TFT)의 이력 현상이 능동형 유기 발광 다이오드(Active-Matrix Organic Light Emitting Diode) 디스플레이 패널을 구동할 경우에, 발생할 수 있는 잔상(Residual Image) 문제를 단위 소자 및 회로에서 실험을 통하여 규명하였다. 게이트 시작 전압을 바꾸어 VGS-ID 특성을 측정할 경우, 게이트 시작 전압이 5V에서 시작한 VGS-ID 곡선이 10V에서 시작한 VGS-ID 곡선에 비해 왼쪽으로 0.15V 이동하였다. 이러한 결과는 게이트 시작 전압의 차이에 의해 발생한 트랩된 전하량(Trapped Charge) 변화로 설명할 수 있다. 또한, 인가하는 게이트 전압 간격을 0.5V에서 0.05V로 감소시켰을 때 전하 디트래핑 비율의 변화(Charge De-trapping Rate)로 인하여, 이력 현상(Hysteresis Phenomenon)으로 인한 단위 소자에서의 문턱전압의 변화가 0.78V에서 0.39V로 감소함을 관찰하였다. 제작된 2-TFT 1-Capacitor의 ANGLED 화소에서 (n-1)번째 프레임에서의 OLED 전류가 (n)번째 프레임에서의 OLED 전류에 35%의 전류오차를 발생시키는 것을 측정 및 분석하였다.

• Current Photovoltaic Research
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• v.2 no.3
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• pp.103-109
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• 2014

Highly efficient hydrogenated nanocrystalline silicon (nc-Si:H) thin-film solar cells were prepared on flexible stainless steel substrates using plasma-enhanced chemical vapor deposition. To enhance the performance of solar cells, material properties of back reflectors, n-doped seed layers and wide bandgap nc-SiC:H window layers were optimized. The light scattering efficiency of Ag back reflectors was improved by increasing the surface roughness of the films deposited at elevated substrate temperatures. Using the n-doped seed layers with high crystallinity, the initial crystal growth of intrinsic nc-Si:H absorber layers was improved, resulting in the elimination of the defect-dense amorphous regions at the n/i interfaces. The nc-SiC:H window layers with high bandgap over 2.2 eV were deposited under high hydrogen dilution conditions. The vertical current flow of the films was enhanced by the formation of Si nanocrystallites in the amorphous SiC:H matrix. Under optimized conditions, a high conversion efficiency of 9.13% ($V_{oc}=0.52$, $J_{sc}=25.45mA/cm^2$, FF = 0.69) was achieved for the flexible nc-Si:H thin-film solar cells.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.729-732
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• 2006

The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.303-310
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• 2008

We fabricated hydrogenated amorphous silicon(a-Si:H) 140 nm thick film on a $180\;nm-SiO_2/Si$ substrate with an inductively-coupled plasma chemical vapor deposition(ICP-CVD) equipment at $250^{\circ}C$. Moreover, 30 nm-Ni film was deposited with a thermal-evaporator sequently. Then the film stack was annealed to induce silicides by a rapid thermal annealer(RTA) at $200{\sim}500^{\circ}C$ in every $50^{\circ}C$ for 30 minuets. We employed a four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), and scanning probe microscope(SPM) in order to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure evolution, and surface roughness, respectively. We confirmed that nano-thick high resistive $Ni_3Si$, mid-resistive $Ni_2Si$, and low resistive NiSi phases were stable at the temperature of <300, $350{\sim}450^{\circ}C$, and >$450^{\circ}C$, respectively. Through SPM analysis, we confirmed the surface roughness of nickel silicide was below 12 nm, which implied that it was superior over employing the glass and polymer substrates.

• Journal of Information Display
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• v.13 no.1
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• pp.51-54
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• 2012

In this study, the bias-temperature stress and current-temperature stress induced by the electrical stabilities of half-Corbino hydrogenated-amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with different gate electrode geometries fabricated on the same substrate were examined. The influence of the gate pattern on the threshold voltage shift of the half-Corbino a-Si:H TFTs is discussed in this paper. The results indicate that the half-Corbino a-Si:H TFT with a patterned gate electrode has enhanced power efficiency and improved aperture ratio when compared with the half-Corbino a-Si:H TFT with an unpatterned gate electrode and the same source/drain electrode geometry.