• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.311-311
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• 2013

The resistance switching memory devices have several advantages to take breakthrough for the limitation of operation speed, retention, and device scale. Especially, the metal-oxide materials such as ZnO are able to fabricate on the flexible and visible transparent plastic substrate. Also, the quantum dots (QDs) embedded in dielectric layer could be improve the ratio between the low and the high resistance becauseof their Coulomb blockade, carrier trap and induced filament path formation. In this study, we irradiated 0.2-MeV-electron beam on the ZnO/QDs/ZnO structure to control the defect and oxygen vacancy of ZnO layer. The metal-oxide QDs embedded in ZnO layer on Pt/glass substrate were fabricated for a memory device and evaluated electrical properties after 0.2-MeV-electron beam irradiations. To formation bottom electrode, the Pt layer (200 nm) was deposited on the glass substrate by direct current sputter. The ZnO layer (100 nm) was deposited by ultra-high vacuum radio frequency sputter at base pressure $1{\times}10^{-10}$ Torr. And then, the metal-oxide QDs on the ZnO layer were created by thermal annealing. Finally, the ZnO layer (100 nm) also was deposited by ultra-high vacuum sputter. Before the formation top electrode, 0.2 MeV liner accelerated electron beams with flux of $1{\times}10^{13}$ and $10^{14}$ electrons/$cm^2$ were irradiated. We will discuss the electrical properties and the physical relationships among the irradiation condition, the dislocation density and mechanism of resistive switching in the hybrid memory device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.

• Journal of the Korea Society of Computer and Information
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• v.22 no.3
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• pp.1-8
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• 2017

In this paper, we propose a new hybrid wear leveling technique for NAND Flash memory, called Time-Aware Wear Leveling (TAWL). Our proposal prolongs the lifetime of NAND Flash memory by using dynamic wear leveling technique which considers the wear level of hot blocks as well as static wear leveling technique which considers the wear level of the whole blocks. TAWL also reduces the overhead of garbage collection by separating hot data and cold data using update frequency rate. We showed that TAWL enhanced the lifetime of NAND flash memory up to 220% compared with previous wear leveling techniques and our technique also reduced the number of copy operations of garbage collections by separating hot and cold data up to 45%.

• International Journal of Aeronautical and Space Sciences
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• v.8 no.2
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• pp.76-81
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• 2007

The fiber reinforced laminated composite structures are very susceptible to be damaged when they are impacted by foreign objects. To increase the impact resistance of the laminated composite structures, shape memory alloy(SMA) thin film is embedded in the structure. For the numerical impact analysis of SMA hybrid composite structures, SMA modeling tool is developed to consider pseudoelastic effect of SMAs. Moreover, the damage analysis is considered using failure criteria and a simple damage model for reasonable impact analysis. The numerical results are verified with the experimental ones. Impact analyses for composite plate with pre-strained SMAs are numerically performed and the damage areas are investigated.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.2
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• pp.101-107
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• 2014

Mobile robots use an environment map of its workspace to complete the surveillance task. However grid-based maps that are commonly used map format for mobile robot navigation use a large size of memory for accurate representation of environment. In this reason, grid-based maps are not suitable for path planning of mobile robots using embedded board. In this paper, we present the path planning algorithm that produce a secure path rapidly. The proposed approach utilizes a hybrid map that uses less memory than grid map and has same efficiency of a topological map. Experimental results show that the fast path planning uses only 1.5% of the time that a grid map based path planning requires. And the results show a secure path for mobile robot.

• Advances in nano research
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• v.14 no.3
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• pp.261-271
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• 2023

The present study follows three main goals. First, an analytical solution with high accuracy is developed to assess the effects of embedding pre-strained shape memory alloy (SMA) wires on the critical buckling temperatures of rectangular sandwich plates made of soft core and graphite fiber/epoxy (GF/EP) face sheets based on piecewise low-order shear deformation theory (PLSDT) using Brinson's model. As the second goal, this study compares the effects of SMAs on the thermal buckling of sandwich plates with those of carbon nanotubes (CNTs). The glass transition temperature is considered as a limiting factor. For each material, the effective ranges of operating temperature and thickness ratio are determined for real situations. The results indicate that depending on the geometric parameters and thermal conditions, one of the SMAs and CNTs may outperform the other. The third purpose is to study the thermal buckling of sandwich plates with advanced hybrid SMA/CNT/GF/EP composite face sheets. It is shown that in some circumstances, the co-incorporation of SMAs and CNTs leads to an astonishing enhancement in the critical buckling temperatures of sandwich plates.

• Journal of the Korea Society of Computer and Information
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• v.18 no.4
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• pp.27-34
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• 2013

Mobile robot has the exploration function in order to perform its own task. Robot exploration can be used in many applications such as surveillance, rescue and resource detection. The workspace that robots performed in was complicated or quite wide, the multi search using the several mobile robots was mainly used. In this paper, we proposed a scheme that all areas are searched for by using one robot. The method to be proposed extract a area that can be explored in the workspace then the robot investigates the area and updates the map at the same time. The explored area is saved as a hybrid map that combines the nice attributes of the grid and topological maps. The robot can produce the safe navigation route without the obstacles by using hybrid map. The proposed hybrid map uses less memory than a grid map, but it can be used for complete coverage with the same efficiency of a topological map. Experimental results show that the proposed scheme can generate a map of an environment with only 6% of the memory that a grid map requires.

• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.293-302
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• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2006.03a
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• pp.563-570
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• 2006

Distributed control architecture is based on sharing control and data between multiple nodes on a network Communication and task sharing can be distributed between multiple control computers. Although many communication protocols exist, such as TCP/IP and UDP, they do not have the determinism that realtime control demands. Fiber-optic reflective shared memory creates the opportunity for realtime distributed control. This architecture allows control and computational tasks to be divided between multiple systems and operate in a deterministic realtime environment. One such shared memory architecture is based on Curtiss-Wright ScramNET family of fiber-optic reflective memory. MTS has built seismic and structural control software and hardware capable of utilizing ScramNET shared memory, opening up infinite possibilities in research and new capabilities in Hybrid and Model-In-The-Loop control.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.