• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 춘계종합학술대회
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• pp.363-365
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• 2003

본 문서는 백프레인(backplane)에서 프로세서 버스(bus)의 데이터 전송 및 수신 특성을 알아보기 위해 HSPICE를 사용하여 시뮬레이션 하였다. 백프레인은 FR-4를 사용하였으며 버스 배선 길이와 스터브(stub) 길이에 대해 데이터 전송속도 특성을 시뮬레이션 하였다. 그리고, 구현 가능한 데이터 전송 및 수신 한계 속도에 대해 검토하였다. 시험결과는 백프레인에서 버스 한계속도에 영향을 주는 것이 버스에 연결된 스터브 길이와 수가 중요한 역할을 함을 알 수 있었다.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2002년도 춘계학술발표논문집
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• pp.215-217
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• 2002

본 논문에서는 CM-MVL(Current Mode Multi-Valued Logic)을 이용한 Host와 LCD Controller 간에 인터페이스 회로를 제안한다. 제안한 회로는 기존의 LVDS(Low Voltage Differential Signaling)과 TMDS(Transition Minimized Differential Signaling)와 같은 전류 특성을 가지며, 3비트 동시 전송이 가능하여 동일한 전송 속도 하에서 보다 많은 데이터를 전송할 수 있다. 그리고 전류에 의한 데이터 전송을 통하여 노이즈에 강한 특성을 나타낸다. 제안한 회로는 HSPICE 시뮬레이션을 통해서 회로의 동작을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.871-874
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• 1998

A new transmission line parameter extraction method of iC interconnects on silicon substrate is presented. To extract the acurate parameters, the silicon substrate effects were taken into account. Since the electromagnetic fields under the silicon substrate are propagated with slow wave mode, effective dielectric constant and different ground plane with the multi-layer dielectric structures were employed for inductance and capacitance matrix determination. Then accurate signal transients simulation were performed with HSPICE by using the parameters. It was shown that the simulation resutls has an excellent agreement with TDR/TDT measurements.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.514-517
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• 1998

This paper proposed a symmetric feedback current enhancement circuit with 1.5V power supply to design a 3$^{rd}$ order butterworth low pass filter. The proposed filter designed on 0.8.mu.m CMOS n-well double poly/double metal process simulated in HSPICE composed of the 3dB frequency enhancement circuit and the unity-gain frequency enhancement circuit. The simulation result on the design filter shows the badnwith of 25MHz, phase of 92.6 .deg. and power consumption of 0.3mW..

• Journal of information and communication convergence engineering
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• 제8권5호
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• pp.566-569
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• 2010

This paper describes the sinusoidal, pulse, triangular oscillator using second generation current conveyor. To obtain the sinusoidal waveform the circuit blocks are constructed by using all pass filter and integrator. The pulse and the triangular waveforms are obtained from the output of sinusoidal oscillator. The peak-to-peak voltages of sinusoidal and triangular waveforms can be easily controlled by the dc offset voltage. Also the output frequency of the oscillator can be controlled by varying passive elements. The designed circuit is verified by HSPICE simulation.

• Journal of information and communication convergence engineering
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• 제6권1호
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• pp.43-46
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• 2008

This paper proposes an advanced test circuit for detecting the connectivity between a drum ring of laser printer and PCB. The detection circuit of charge sharing is proposed, which minimizes the influences of internal parasitic capacitances. The test circuit is composed of precharge circuit, analog comparator, level shifter. Its functional operation is verified using $0.6{\mu}m$ 3.3V/40V CMOS process parameter by HSPICE. Access time is100ns. Layout of the drum contact test circuit is $465{\mu}m\;{\times}\;117{\mu}m$.

• Journal of Information Display
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• 제6권1호
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• pp.17-21
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• 2005

We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.69-72
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• 2002

This paper proposed a new charge-shared switching MDAC for a pipelined A/D converter The proposed architecture accomplishes the same function of a conventional multiplying-digital-to-analog converter (MDAC). By adopting the proposed scheme, about 40% of the total capacitances could be reduced and the speed of the MDAC increases. The performance of the charge-shared switching MDAC has been Proved by HSPICE simulations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1292-1295
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• 2002

The performance of the LSI improved drastically due to the progress of the semiconductor manufacturing technology in recent years. However, a new problem such as wiring delay and complication inside the LSI occurs. The study to solve these problems with much research organization is been doing. We tried to solve of these problems by using the neuron MOS transistor with 4-valued signal in addition to the binary signal. In this paper, We present, method which realizes 4-valued logic function. And, a designed circuit, is verified by using HSPICE.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.