• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.2B
• /
• pp.1-10
• /
• 2005

TCP/IP protocols have been implemented in software program running on CPU in end systems. As the increased demand of fast protocol processing, it is required to implement the protocols in hardware, and Host Interface is responsible for communication between external CPU and the hardware blocks of TCP/IP implementation. The Host Interface follows AMBA AHB specification for the communication with external world. For control flow, the Host Interface behaves as a slave of AMBA AHB. Using internal Command/status Registers, the Host Interface receives commands from CPU and transfers hardware status and header information to CPU. On the other hand, the Host Interface behaves as a master for data flow. Data flow has two directions, Receive Flow and Transmit Flow. In Receive Flow, using internal RxFIFO, the Host Interface reads data from UDP FIFO or TCP buffer and transfers data to external RAM for CPU to read. For Transmit Flow, the Host Interface reads data from external RAM and transfers data to UDP buffer or TCP buffer through internal TxFIFO. TCP/IP hardware blocks generate packets using the data and transmit. Buffer Descriptor is one of the Command/Status Registers, and the information stored in Buffer Descriptor is used for external RAM access. Several testcases are designed to verify TCP/IP functions. The Host Interface is synthesized using the 0.18 micron technology, and it results in 173 K gates including the Command/status Registers and internal FIFOs.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.855-858
• /
• 2003

TCP/IP 를 포함하는 데이터 네트워킹 프로토콜을 구현함에 있어, 기존에는 소프트웨어 방식으로 구현되었던 모듈들을 하드웨어로 구현하는 프로젝트를 수행하면서, CPU 와 하드웨어 모듈과의 통신을 중계하는 모듈을 구현하였다. 본 논문에서는 TCP/IP 하드웨어와 CPU 와의 통신을 위한 Host Interface 의 기능에 대해 다루고 구현 방식을 Control flow와 Data flow의 입장에서 설명하였다. 우선, Host Interface 의 기능을 설명하고 Host Interface 의 입출력 신호를 정의하였다. Host Interface에서 이루어지는 CPU와 하드웨어 모듈간의 통신을 제어정보 흐름과 데이터정보 흐름으로 나누고 제어흐름을 위해서는 Command/Status Register 를 두었고, 데이터 흐름을 위해서는 CPU와 데이터 RAM 사이에 FIFO 를 두어 데이터의 흐름이 신속히 이루어지도록 하였다. 끝으로 Host Interface 와 주변 모듈들간의 통신에 대한 Testcases에 대해서도 다루었다.

• IMMUNE NETWORK
• /
• v.13 no.5
• /
• pp.163-167
• /
• 2013

The dynamics of the virus-host interface in the response to respiratory virus infection is not well-understood; however, it is at this juncture that host immunity to infection evolves. Respiratory viruses have been shown to modulate the host response to gain a replication advantage through a variety of mechanisms. Viruses are parasites and must co-opt host genes for replication, and must interface with host cellular machinery to achieve an optimal balance between viral and cellular gene expression. Host cells have numerous strategies to resist infection, replication and virus spread, and only recently are we beginning to understand the network and pathways affected. The following is a short review article covering some of the studies associated with the Tripp laboratory that have addressed how respiratory syncytial virus (RSV) operates at the virus-host interface to affects immune outcome and disease pathogenesis.

• KIISE Transactions on Computing Practices
• /
• v.23 no.2
• /
• pp.97-103
• /
• 2017

Many hardware-based regular expression matching architectures have been proposed for high-performance matching. In particular, regular expression processors, which perform pattern matching by treating the regular expressions as the instruction sequence like general purpose processors, have been proposed. After instruction sequence and data are provided in the instruction memory and data memory, respectively, a regular expression processor can perform pattern matching. To use a regular expression processor as a coprocessor, we need the host interface to transfer the instruction and data into the memory of a regular expression processor. In this paper, we design and implement the host interface between a host and a regular expression processor in the DE1-SoC board and the application program interface. We verify the operations of the host interface and a regular expression processor by executing the application programs which perform pattern matching using the application program interface.

• Journal of Plant Biology
• /
• v.36 no.3
• /
• pp.285-292
• /
• 1993

Cellular compatibility in the self-parasitism of Cuscuta australis R. Brown was studied at the ultrastructural level. The front cells of the haustorium penetrated the host stems independently grew within the host tissues and transformed into elongate, filamentous hyphae. Each hyphal cells contained a large nucleus and dense cytoplasm with abundant cell organelles. Multilamellar structures were contained in the cytoplasm and cell walls of the penetrating hyphal cells. When the hyphal cells did not yet invade the host cells, the middle lamella and the fused cellulosic cell walls of the two partners at the host-parasite interface were preserved well. As the invasion of the parasitic hyphal cells progressed, however, the middle lamella was not found at the interface and the host cell walls and plasma membranes were partially broken down. A hyphal cell penetrated deeply into the host cell had a more darkly stained cytoplasm with numerous of cell organelles. In the host cells attacked by the hyphal cells the limiting membranes of plastids were broken down and several vesicles were arrayed near the cell walls. No plasmodesmatal connections between the host and parasite cell walls were found; however, half-plasmodesmata were observed frequently on the side of the hyphal cell walls. These results suggested that the compatibility response in the self-parasitism of Cuscuta was expressed by cell walls, not by plasmodesmata, between the host and the parasite cells.

• International Journal of Internet, Broadcasting and Communication
• /
• v.13 no.2
• /
• pp.27-35
• /
• 2021

NAND flash memory-based SSD needs an internal software, Flash Translation Layer(FTL) to provide traditional block device interface to the host because of its physical constraints, such as erase-before-write and large erase block. However, because useful host-side information cannot be delivered to FTL through the narrow block device interface, SSDs suffer from a variety of problems such as increasing garbage collection overhead, large tail-latency, and unpredictable I/O latency. Otherwise, the new type of SSD, open-channel SSD exposes the internal structure of SSD to the host so that underlying NAND flash memory can be managed directly by the host-level FTL. Especially, I/O data classification by using host-side information can achieve the reduction of garbage collection overhead. In this paper, we propose a new scheme to reduce garbage collection overhead of open-channel SSD by separating the journal from other file data for the journaling filesystem. Because journal has different lifespan with other file data, the Write Amplification Factor (WAF) caused by garbage collection can be reduced. The proposed scheme is implemented by modifying the host-level FTL of Linux and evaluated with both Fio and Filebench. According to the experiment results, the proposed scheme improves I/O performance by 46%~50% while reducing the WAF of open-channel SSDs by more than 33% compared to the previous one.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1836-1839
• /
• 2005

We have developed Ethernet based real-time communication systems called "Vnet/IP" for DCS which is the control system for process automation. This paper describes the features and the technologies of the ASIC which is utilized in the communication interface hardware for Vnet/IP. Vnet/IP has been developed for mission-critical communications. Hence it has real-time feature, high reliability and precise time synchronization capability. At the same time, it is able to deal with standard protocols without influence on mission-critical communications. The communication interface hardware has a host interface and dual redundant network interfaces. The host interface can be chosen PCI-bus or R-bus which is the proprietary internal bus developed for the high reliable redundant controller. Each network interface is a RJ45 connection with 1Gbps maximum in compliance with IEEE802.3.

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.665-668
• /
• 2003

In this paper, we have designed and implemented the RAID controller board which connects to the host computer with serial ATA interface and connects to the disks with parallel ATA interface. Serial ATA interface is proposed to overcome the design limitation of parallel ATA while enabling the storage interface to scale with the slowing media rate demands for PC platforms. Serial ATA is to replace parallel ATA with the compatibility with existing operating systems and drivers, adding performance headroom for years to come. It Moreover, serial ATA provides even faster transfer rate of 150 Mbytes/s which is larger than that of current parallel ATA. The RAID controller board designed in this paper combines up to 4 disks with parallel ATA interface, and connects to PC host computer with serial ATA interface. We have implemented RAID controller using Verilog HDL language with FPGA chip. The RAID controller supports RAID level 0 and 1 functionality. Experimently, the average read/write performance of parallel ATA interface is about 30 Mbytes/s. Therefore, when 4 parallel disks is connected to the RAID controller board, we can get almost full throughput of serial ATA protocol using the RAID level 0 configuration with 4 disks.

• Journal of Information Processing Systems
• /
• v.4 no.4
• /
• pp.133-144
• /
• 2008

Clusters have become a popular alternative for building high-performance parallel computing systems. Today's high-performance system area network (SAN) protocols such as VIA and IBA significantly reduce user-to-user communication latency by implementing protocol stacks outside of operating system kernel. However, emerging parallel applications require a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) make up a large portion of overall communication latency, the reduction of data transfer time is crucial for achieving low-latency communication. In this paper, Eager Data Transfer (EDT) mechanism is proposed to reduce the time for data transfers between the host and network interface. The EDT employs cache coherence interface hardware to directly transfer data between the host and NI. An EDT-based network interface was modeled and simulated on the Linux-based, complete system simulation environment, Linux/SimOS. Our simulation results show that the EDT approach significantly reduces the data transfer time compared to DMA-based approaches. The EDTbased NI attains 17% to 38% reduction in user-to-user message time compared to the cache-coherent DMA-based NIs for a range of message sizes (64 bytes${\sim}$4 Kbytes) in a SAN environment.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.414-420
• /
• 2005

The ShortStack Micro Server enables any product that contains a microcontroller or microprocessor to quickly and inexpensively become a networked, Internet-accessible device. The ShortStack Micro Server provides a simple way to add LonWorks networking to new or existing smart devices. . It implements the LonTalk protocol and provides the physical interface with the LonWorks communication. The ShortStack host processor can be an 8, 16, or 32-bit microprocessor or microcontrollers. The ShortStack API and driver typically require about 4kbytes of program memory on the host processor and less than 200 bytes of RAM. The interface between host processor and the ShortStack Micro Server may be a Serial Communication Interface (SCI). The LonWorks control module with a high performance is developed, which is composed of the 8 bit PIC Microprocessor for host processor and the smart neuron chip for the ShortStack Micro Server. This intelligent control board is verified as proceeding the various function tests from experimental system with an boost pump and inverter driving systems. It is also confirmed that the developed control module provides stably 0-10VDC linear signal to the input signal of inverter driving system for varying the induction motor speed. Thus, the experimental results show that the fabricating intelligent board carried out very well the various functions in the wide operating ranges of boost pump system. This developed control module expect to apply to industrial fields to require the comparatively exact control and monitoring such as multi-motor driving system with inverter, variable air volume system and the boost pump water supply systems.