• 한국안전학회지
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• 제38권3호
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• pp.27-34
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• 2023

With the technological development of the semiconductor industry, the roles of electrical and thermal energy supply and control of semiconductor equipment in ultrafine processes have become very important. However, instances of electrical fires in the chiller heater, which is used for cooling in the semiconductor manufacturing process, are increasing. A fire occurs in combustibles due to high heat at the connection part of the chiller heater, that is, when the number of electrical wires in the connection part is reduced or when the wires are completely disconnected. In this study, the temperature characteristics were compared and analyzed through experiments and 3D simulations. The number of electrical wires, which is the connection part of the chiller heater, was reduced by 90%, 50%, 30%, 10%, and 5%, and the wires were completely disconnected. When the number of electrical wires was reduced by 5%, heat of up to 80℃ was generated, which is a relatively high temperature but insufficient to cause a fire in combustibles. Complete disconnection occurred due to the vibration of the motor and other components, and sparks and arcs were generated, resulting in a rapid increase in temperature to up to 680℃. When completely disconnected, the temperature increase was sufficient to cause a fire in the combustibles covering the terminal block. Therefore, in this study, the causes of electrical fires in chiller heaters were investigated and preventive measures were proposed by analyzing abnormal signals and thermal characteristics caused by the electrical wiring being reduced and completely disconnected.

• 반도체디스플레이기술학회지
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• 제12권2호
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• pp.93-98
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• 2013

Nanoimprint lithography (NIL) is a next generation technology for fabrication of micrometer and nanometer scale patterns. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. To successfully imprint a nanosized pattern with the thermal NIL, the process conditions such as temperature and pressure should be appropriately selected. This starts with a clear understanding of polymer material behavior during the thermal NIL process. In this paper, a filling process of the polymer resist into nanometer scale cavities during the thermal NIL at the temperature range, where the polymer resist shows the viscoelastic behaviors with consideration of stress relaxation effect of the polymer. In the simulation, the filling process and the residual layer formation are numerically investigated. And the effects of pressure and temperature on NIL process, specially the residual layer formation are discussed.

• 반도체디스플레이기술학회지
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• 제22권1호
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• pp.28-32
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• 2023

Recently, the use of stable lithium nanostructures as substrates and electrodes for secondary batteries can be a fundamental alternative to the development of next-generation system semiconductor devices. However, lithium structures pose safety concerns by severely limiting battery life due to the growth of Li dendrites during rapid charge/discharge cycles. Also, enabling long cyclability of high-voltage oxide cathodes is a persistent challenge for all-solid-state batteries, largely because of their poor interfacial stabilities against oxide solid electrolytes. For the development of next-generation system semiconductor devices, solid electrolyte nanostructures, which are used in high-density micro-energy storage devices and avoid the instability of liquid electrolytes, can be promising alternatives for next-generation batteries. Nevertheless, poor lithium ion conductivity and structural defects at room temperature have been pointed out as limitations. In this study, a low-dimensional Graphene Oxide (GO) structure was applied to demonstrate stable operation characteristics based on Li+ ion conductivity and excellent electrochemical performance. The low-dimensional structure of GO-based solid electrolytes can provide an important strategy for stable scalable solid-state power system semiconductor applications at room temperature. The device using uncoated bare NCA delivers a low capacity of 89 mA h g-1, while the cell using GO-coated NCA delivers a high capacity of 158 mA h g−1 and a low polarization. A full Li GO-based device was fabricated to demonstrate the practicality of the modified Li structure using the Li-GO heterointerface. This study promises that the lowdimensional structure of Li-GO can be an effective approach for the stabilization of solid-state power system semiconductor architectures.

• 반도체디스플레이기술학회지
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• 제17권1호
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• pp.35-39
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• 2018

This paper deals with the relaxation of singular stresses developed in an epoxy adhesive at high temperature. The interface stresses are analyzed using BEM. The adhesive employed in this study is an epoxy which can be cured at room temperature. The adhesive is assumed to be linearly viscoelastic. First, the distribution of the interface stresses developed in the adhesive layer under the uniform tensile stress has been calculated. The singular stress has been observed near the interface corner. Such singular stresses near the interface corner may cause epoxy layer separated from adherent. Second, the interfacial thermal stress has been investigated. The uniform temperature rise can relieve the stress level developed in the adhesive layer under the external loading, which can be viewed as an advantage of thermal loading. It is also obvious that temperature rise reduces the bonding strength of the adhesive layer. Experimental evaluation is required to assess a trade-off between the advantageous and deleterious effects of temperature.

• 한국산업보건학회지
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• 제24권3호
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• pp.272-280
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• 2014

Objectives: The purpose of this study was to evaluate the characteristics of worker exposure to hazardous chemical substances and propose the direction of work environment management for protecting worker's health in the semiconductor assembly process. Methods: Four assembly lines at two semiconductor manufacturing companies were selected for this study. We investigated the types of chemicals that were used and generated during the assembly process, and evaluated the workers' exposure levels to hazardous chemicals such as benzene and formaldehyde and the current work environment management in the semiconductor assembly process. Results: Most of the chemicals used at the assembly process are complex mixtures with high molecular weight such as adhesives and epoxy molding compounds(EMCs). These complex mixtures are stable when they are used at room temperature. However workers can be exposed to volatile organic compounds(VOCs) such as benzene and formaldehyde when they are used at high temperature over $100^{\circ}C$. The concentration levels of benzene and formaldehyde in chip molding process were higher than other processes. The reason was that by-products were generated during the mold process due to thermal decomposition of EMC and machine cleaner at the process temperature($180^{\circ}C$). Conclusions: Most of the employees working at semiconductor assembly process are exposed directly or indirectly to various chemicals. Although the concentration levels are very lower than occupational exposure limits, workers can be exposed to carcinogens such as benzene and formaldehyde. Therefore, workers employed in the semiconductor assembly process should be informed of these exposure characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.495-502
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• 2014

Fast recovery diodes (FRDs) were developed using the $p^{{+}{+}}/n^-/n^{{+}{+}}$ epitaxial layers grown by low temperature epitaxy technology. We investigated the effect of electrostatic discharge (ESD) stresses on their electrical and switching properties using current-voltage (I-V) and reverse recovery time analyses. The FRDs presented a high breakdown voltage, >450 V, and a low reverse leakage current, < $10^{-9}$ A. From the temperature dependence of thermal activation energy, the reverse leakage current was dominated by thermal generation-recombination and diffusion, respectively, at low and high temperature regions. By virtue of the abrupt junction and the Pt drive-in for the controlling of carrier lifetime, the soft reverse recovery behavior could be obtained along with a well-controlled reverse recovery time of 21.12 ns. The FRDs exhibited excellent ESD robustness with negligible degradations in the I-V and the reverse recovery characteristics up to ${\pm}5.5$ kV of HBM and ${\pm}3.5$ kV of IEC61000-4-2 shocks. Likewise, transmission line pulse (TLP) analysis reveals that the FRDs can handle the maximum peak pulse current, $I_{pp,max}$, up to 30 A in the forward mode and down to - 24 A in the reverse mode. The robust ESD property can improve the long term reliability of various power applications such as automobile and switching mode power supply.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2004년도 춘계학술대회 발표 논문집
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• pp.123-128
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• 2004

Semiconductor Wet Station has a very important place in semiconductor process. It is important that to discharge chemical with fit concentration and temperature using chemical supply system for clean process. The chemical supply system which is used currently is not only difficult to make a fit mixing rate of chemical which is need in clean process, but also difficult to make fit concentration and temperature. Moreover, it has high stability but it is inefficient spatially because its volume is great. We propose In-line System to improve system with implement analysis of fluid and thermal transfer on chemical supply system and understand problem of system.

• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• 반도체디스플레이기술학회지
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• 제16권4호
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• pp.68-74
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• 2017

Nanoimprint lithography (NIL) is a next generation technology for fabrication of micrometer and nanometer scale patterns. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. Up to now there have been a lot of researches on thermal NIL, but most of them have been focused on polymer deformation in the molding process and there are very few studies on the cooling and demolding process. In this paper a cooling process of the polymer resist in thermal NIL is analyzed with finite element method. The modeling of cooling process for mold, polymer resist and substrate is developed. And the cooling process is numerically investigated with the effects of imprinting temperature and residual layer thickness of polymer resist on stress distribution of the polymer resist. The results show that the lower imprinting temperature, the higher the maximum von Mises stress and that the thicker the residual layer, the greater maximum von Mises stress.

• Journal of the Korean Physical Society
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• 제73권9호
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• pp.1356-1361
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• 2018

Replacing conventional Si diodes with SiC diodes in Si insulated gate bipolar transistor (IGBT) modules is advantageous as it can reduce power losses significantly. Also, the fast switching nature of the SiC diode will allow Si IGBTs to operate at their full high-switching-speed potential, which at present conventional Si diodes cannot do. In this work, the electrical test results for Si-IGBT/4HSiC-Schottky hybrid substrates (hybrid SiC substrates) are presented. These substrates are built for two voltage ratings, 1.7 kV and 3.3 kV. Comparisons of the 1.7 kV and the 3.3 kV Si-IGBT/Si-diode substrates (Si substrates) at room temperature ($20^{\circ}C$, RT) and high temperature ($H125^{\circ}C$, HT) have shown that the switching losses in hybrid SiC substrates are miniscule as compared to those in Si substrates but necessary steps are required to mitigate the ringing observed in the current waveforms. Also, the effect of design variations on the electrical performance of 1.7 kV, 50 A diodes is reported here. These variations are made in the active and termination regions of the device.