• Title/Summary/Keyword: high-speed mobile

Search Result 661, Processing Time 0.028 seconds

A 12b 100MS/s 1V 24mW 0.13um CMOS ADC for Low-Power Mobile Applications (저전력 모바일 응용을 위한 12비트 100MS/s 1V 24mW 0.13um CMOS A/D 변환기)

  • Park, Seung-Jae;Koo, Byeong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.47 no.8
    • /
    • pp.56-63
    • /
    • 2010
  • This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

An Analysis of Satellite Communications System structure for NCW (NCW대비 군 위성통신 구조 분석)

  • Park, Woo-Chul;Cha, Jae-Ryong;Kim, Jae-Hyun
    • Journal of Satellite, Information and Communications
    • /
    • v.4 no.1
    • /
    • pp.1-7
    • /
    • 2009
  • As the information age comes out, the aspect of future war brings about the many changes in terms of war-fighting environment. Accordingly, information superiority and intelligence-centric warfare have been important and new war-fighting concept such as NCW(network centric warfare) have been turned up. This paper proposed all-weather core-strategy communications systems guaranteeing not only the real-time transmission of the information collected in a battlefield and expansion, automation, and rapidity of a battlefield but also broadband, mobility, survivability, and flexibility. The proposed military satellite communications system is classified into wideband mass capacity link, survivability, and the system supporting OTM(on the move) communication for the real-time transmission of battlefield information. This paper analyzed the essential operation concepts and core schemes of the U.S. Army's next generation system, TSAT(Transformational Satellite Communication System). Base on the analysis results, this paper proposed that the architecture of next generation military satellite communications systems for NCW have to provide the data rate, anti-jamming capability, network control and management capability which are optimally adaptable for the wireless channel environments such as jamming and interference and to support the variety of platforms like high-speed mobile vehicles, micromini devices, super-high speed unmanned aerial vehicles. Finally, this paper also proposed that next generation military satellite communications systems need the technologies such as the adaptable multi-antenna, laser link, and next-generation anti-jamming waveform.

  • PDF

Development of Attitude Heading Reference System based on MEMS for High Speed Autonomous Underwater Vehicle (고속 자율 무인잠수정 적용을 위한 MEMS 기술기반 자세 측정 장치 개발)

  • Hwang, A-Rom;Ahn, Nam-Hyun;Yoon, Seon-Il
    • Journal of the Korean Society of Marine Environment & Safety
    • /
    • v.19 no.6
    • /
    • pp.666-673
    • /
    • 2013
  • This paper proposes the performance evaluation test of attitude heading reference system (AHRS) suitable for small high speed autonomous underwater vehicle(AUV). Although IMU can provides the detail attitude information, it is sometime not suitable for small AUV with short operation time in view of price and the electrical power consumption. One of alternative for tactical grade IMU is the AHRS based micro-machined electro mechanical system(MEMS) which can overcome many problems that have inhibited the adoption of inertial system for small AUV such as cost and power consumption. A cost effective and small size AHRS which incorporates measurements from 3-axis MEMS gyroscopes, accelerometers, and 3-axis magnetometers has been developed to provide a complete attitude solution for AUV and the attitude calculation algorithm is derived based the coordinate transform equation and Kalman filter. The developed AHRS was validated through various performance tests as like the magnetometer calibration, operating experiments using land mobile vehicle and flight motion simulator (FMS). The test of magnetometer calibration shows the developed MEMS AHRS is robust to the external magent field change and the test with land vehicle proves the leveling error of developed MEMS AHRS is below $0.5^{\circ}/hr$. The results of FMS test shows the fact that AHRS provides the measurement with $0.5^{\circ}/hr$ error during 5 minutes operation time. These results of performance evaluation tests showed that the developed AHRS provides attitude information which error of roll and pitch are below $1^{\circ}$ and the error of yaw is below $5^{\circ}$ and satisfies the required specification. It is expected that developed AHRS can provide the precise attitude measurement under sea trial with real AUV.

The viterbi decoder implementation with efficient structure for real-time Coded Orthogonal Frequency Division Multiplexing (실시간 COFDM시스템을 위한 효율적인 구조를 갖는 비터비 디코더 설계)

  • Hwang Jong-Hee;Lee Seung-Yerl;Kim Dong-Sun;Chung Duck-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.42 no.2 s.332
    • /
    • pp.61-74
    • /
    • 2005
  • Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

Wideband Class-J Power Amplifier Design Using Internal Matched GaN HEMT (내부정합된 GaN HMET를 이용한 광대역 J-급 전력증폭기 설계)

  • Lim, Eun-Jae;Yoo, Chan-Se;Kim, Do-Gueong;Sun, Jung-Gyu;Yoon, Dong-Hwan;Yoon, Seok-Hui;Rhee, Young-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.28 no.2
    • /
    • pp.105-112
    • /
    • 2017
  • In order to satisfy the diffusion of multimedia service in mobile communication and the demand for high-speed communication, it is essential to modify and improve high efficiency, wideband and nonlinear characteristic of multiband power amplifier. This research is designed to implement a single-stub matching circuit as a 2nd harmonic one that meets conditions of the Class-J power amplifier. Low characteristic impedance of the single-stub line is necessary to suit conditions of wideband Class-J. This research uses ceramic substrates having high permittivity to implement the single-stub line with low characteristic impedance, which eventually results in an amplifier satisfying the output impedance terms of Class-J in wideband frequency range. This result attributes to use of GaN HEMT packaged with a 2nd harmonic matching circuit and external fundamental circuit. The measurement results of the Class-J amplifier confirms the following characteristics: more than output power of 50 W(47 dBm) in bandwidth of 1.8~2.7 GHz(0.9GHz), maximum drain efficiency of 72.6 %, and maximum PAE characteristic of 66.5 %.

A Study on the Establishment of Entropy Source Model Using Quantum Characteristic-Based Chips (양자 특성 기반 칩을 활용한 엔트로피 소스 모델 수립 방법에 관한 연구)

  • Kim, Dae-Hyung;Kim, Jubin;Ji, Dong-Hwa
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2021.10a
    • /
    • pp.140-142
    • /
    • 2021
  • Mobile communication technology after 5th generation requires high speed, hyper-connection, and low latency communication. In order to meet technical requirements for secure hyper-connectivity, low-spec IoT devices that are considered the end of IoT services must also be able to provide the same level of security as high-spec servers. For the purpose of performing these security functions, it is required for cryptographic keys to have the necessary degree of stability in cryptographic algorithms. Cryptographic keys are usually generated from cryptographic random number generators. At this time, good noise sources are needed to generate random numbers, and hardware random number generators such as TRNG are used because it is difficult for the low-spec device environment to obtain sufficient noise sources. In this paper we used the chip which is based on quantum characteristics where the decay of radioactive isotopes is unpredictable, and we presented a variety of methods (TRNG) obtaining an entropy source in the form of binary-bit series. In addition, we conducted the NIST SP 800-90B test for the entropy of output values generated by each TRNG to compare the amount of entropy with each method.

  • PDF

End to End Model and Delay Performance for V2X in 5G (5G에서 V2X를 위한 End to End 모델 및 지연 성능 평가)

  • Bae, Kyoung Yul;Lee, Hong Woo
    • Journal of Intelligence and Information Systems
    • /
    • v.22 no.1
    • /
    • pp.107-118
    • /
    • 2016
  • The advent of 5G mobile communications, which is expected in 2020, will provide many services such as Internet of Things (IoT) and vehicle-to-infra/vehicle/nomadic (V2X) communication. There are many requirements to realizing these services: reduced latency, high data rate and reliability, and real-time service. In particular, a high level of reliability and delay sensitivity with an increased data rate are very important for M2M, IoT, and Factory 4.0. Around the world, 5G standardization organizations have considered these services and grouped them to finally derive the technical requirements and service scenarios. The first scenario is broadcast services that use a high data rate for multiple cases of sporting events or emergencies. The second scenario is as support for e-Health, car reliability, etc.; the third scenario is related to VR games with delay sensitivity and real-time techniques. Recently, these groups have been forming agreements on the requirements for such scenarios and the target level. Various techniques are being studied to satisfy such requirements and are being discussed in the context of software-defined networking (SDN) as the next-generation network architecture. SDN is being used to standardize ONF and basically refers to a structure that separates signals for the control plane from the packets for the data plane. One of the best examples for low latency and high reliability is an intelligent traffic system (ITS) using V2X. Because a car passes a small cell of the 5G network very rapidly, the messages to be delivered in the event of an emergency have to be transported in a very short time. This is a typical example requiring high delay sensitivity. 5G has to support a high reliability and delay sensitivity requirements for V2X in the field of traffic control. For these reasons, V2X is a major application of critical delay. V2X (vehicle-to-infra/vehicle/nomadic) represents all types of communication methods applicable to road and vehicles. It refers to a connected or networked vehicle. V2X can be divided into three kinds of communications. First is the communication between a vehicle and infrastructure (vehicle-to-infrastructure; V2I). Second is the communication between a vehicle and another vehicle (vehicle-to-vehicle; V2V). Third is the communication between a vehicle and mobile equipment (vehicle-to-nomadic devices; V2N). This will be added in the future in various fields. Because the SDN structure is under consideration as the next-generation network architecture, the SDN architecture is significant. However, the centralized architecture of SDN can be considered as an unfavorable structure for delay-sensitive services because a centralized architecture is needed to communicate with many nodes and provide processing power. Therefore, in the case of emergency V2X communications, delay-related control functions require a tree supporting structure. For such a scenario, the architecture of the network processing the vehicle information is a major variable affecting delay. Because it is difficult to meet the desired level of delay sensitivity with a typical fully centralized SDN structure, research on the optimal size of an SDN for processing information is needed. This study examined the SDN architecture considering the V2X emergency delay requirements of a 5G network in the worst-case scenario and performed a system-level simulation on the speed of the car, radius, and cell tier to derive a range of cells for information transfer in SDN network. In the simulation, because 5G provides a sufficiently high data rate, the information for neighboring vehicle support to the car was assumed to be without errors. Furthermore, the 5G small cell was assumed to have a cell radius of 50-100 m, and the maximum speed of the vehicle was considered to be 30-200 km/h in order to examine the network architecture to minimize the delay.

Design of a Low-Power LDPC Decoder by Reducing Decoding Iterations (반복 복호 횟수 감소를 통한 저전력 LDPC 복호기 설계)

  • Lee, Jun-Ho;Park, Chang-Soo;Hwang, Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.32 no.9C
    • /
    • pp.801-809
    • /
    • 2007
  • LDPC Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

Distributed Power Control with Reference Model in the CDMA cellular system (기준모델을 이용한 CDMA 분산전력제어)

  • Lee, Moo-Young;Oh, Do-Chang;Kwon, Woo-Hyen
    • The KIPS Transactions:PartC
    • /
    • v.10C no.5
    • /
    • pp.617-624
    • /
    • 2003
  • This paper proposes a modified DCPC (Distributed Constrained Power Control, M-DCPC) algorithm that can improve the performance of a CDMA power control system. The control performance of the proposed method is verified using two performance measures : the SIR response of each mobile and the outage probability in a cell. As regards the SIR response, in simulations, the M-DCPC algorithm has shown a faster convergence and lower overshoot in transient time than the other power control algorithms when the desired SIR value was varying. For the outage probability. M-DCPC converged to a fixed outage rate faster than CSOPC while also maintaining the system capacity to make as high a connection as CSOPC. In particular, when the desired SIR was varying, CSOPC showed an abrupt outage probability increase during the desired SIR Increase, yet M-DCPC was unaffected.

Error Recovery Schemes with IPv6 Header Compression (IPv6 헤더 압축에서의 에러 복구방안)

  • Ha Joon-Soo;Choi Hyun-Jun;Seo Young-Ho;Kim Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.10 no.7
    • /
    • pp.1237-1245
    • /
    • 2006
  • This paper presented a hardware implementation of ARIA, which is a Korean standard l28-bit block cryptography algorithm. In this work, ARIA was designed technology-independently for application such as ASIC or core-based designs. ARIA algorithm was fitted in FPGA without additional components of hardware or software. It was confirmed that the rate of resource usage is about 19% in Altera EPXAl0F1020CI and the resulting design operates stably in a clock frequency of 36.35MHz, whose encryption/decryption rate was 310.3Mbps. Consequently, the proposed hardware implementation of ARIA is expected to have a lot of application fields which need high speed process such as electronic commerce, mobile communication, network security and the fields requiring lots of data storing where many users need processing large amount of data simultaneously.