• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.364-371
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• 2007

In this paper, the design and implementation of high-power PIN diode switch modules and high-speed switch driver circuits are presented for Wibro base stations. To prevent isolation degradation due to parasitic inductances of conventional packaged PIN diodes and to improve power handling capabilities of the switch modules, bare diode chips are used and carefully placed in a PCB layout, which makes bonding wire inductances to be absorbed in the impedance of a transmission line. The switch module is designed and implemented to have a maximum performance while using a minimum number of the diodes. It shows an insertion loss of ${\sim}0.84\;dB$ and isolation of 80 dB or more at 2.35 GHz. The switch driver circuit is also fabricated and measured to have a switching speed of ${\sim}200\;nsec$. The power handling capability test demonstrates that the module operates normally even under a digitally modulated 70 W RF signal stress.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.3
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• pp.292-297
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• 1987

High-speed GaAs IC Logic Gates being widely studied and developed in the develped countries were reanalysed and reexamined through SPICE simulations. And, furthermore, the detailed examinations of their characteristics such as operation characteristics and conditions, integration densities, service-ableness, and the limitation of both fabrication and application, give us a clue of the feasibility and application of them in the real integrated circuits. This paper will provide a reasonably good guide to set-up one of goals or future development of high-speed GaAs IC's being led by the goverment recently in our country.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1559-1562
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• 2002

This paper describes a 0.13um ultra-high speed 1Mb CMOS SRAM macro with 1.7ns access time. It achieves ultra-high speed operation using two novel approaches. First, it uses process insensitive sense amplifier (Double-Equalized Sense Amplifier) which improves voltage offset by about 10 percent. Secondly, it uses new replica-based sense amplifier driver which improves bit- line evaluation time by about 10 percent compared to the conventional technique. The various memory macros can be generated automatically by using a compiler, word-bit size from 64kb to 1 Mb including repairable redundancy circuits.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.18 no.5
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• pp.491-497
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• 2009

Of all of pneumatic components utilized in the make up of pneumatic circuits on either automatic assembly machine or industrial equipment, the pneumatic cylinder is more oriented toward being a structural as well as a pneumatic member. The structural design must be based to a large degree on the end of application of the cylinder on the equipment it is operating. In this paper, design studies of a double-acting pneumatic cushion type cylinder with low-friction and high-speed driving have been developed. Of interest here is to investigate the stress and strain analysis of cylinder tube, piston rod, end cover, and to analyze the buckling of piston rod. A finite element analysis is carried out to compute the distribution of the displacement, stress and safety factors by using ANSYS. As a result, the structural safety factors of each parts in pneumatic cushion cylinder are evaluated and confirmed at the design specifications.

• Progress in Superconductivity and Cryogenics
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• v.8 no.1
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• pp.26-28
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• 2006

The development technique of digital logic using CMOS device is close reached several limitations These make technical needs that are ultra high speed superconductive systems based on CMOS silicon digital computing technique. Comparing digital logic based on silicon CMOS, the computing technique based on ultra high speed superconductive systems has many advantages which are ultra low power consumption, ultra high operation speed. etc. It is estimated that features like these increasingly improve the possibility of ultra low power and ultra superconductive systems. In this paper digital logics of current CMOS technique and RSFQ superconductive technique are compared with and analyzed.

• The Journal of Information Technology
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• v.2 no.2
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• pp.145-161
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• 1999

This paper proposes a high speed back propagation neural networks which uses the residue number system. making the high speed operation possible without carry propagation Consisting of MAC(Multiplication and Accumulation) operator unit using Residue number system and sigmoid function operator unit using Mixed Residue Conversion is designed, The Designed circuits are descripted by VHDL and synthesized by Compass tools. Result of simulations shows that critical path delay time is about 19nsec and the size can be reduced to 40% compared to the neural networks implemented by the real number operation unit. The proposed design circuits can be implemented in parallel distributed processing system with desired real time processing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.43-49
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• 2000

We proposed ADD(Alternate Directional Delay) circuit technique as the DLL(Delay Locked Loop) circuits which technique is established the data valid window(tDV) in DDR(Double Data Rate) Synchronous DRAM. This technique could be decrease area-overhead which it could generated bidirectional clock simultaneously using only one delay chain block. In this paper for high speed memory with relatively small size. This technique decreased area-overhead more 2 times than SMD(Synchronous Mirror Delay) technique. ADD technique has 50ps-140ps jitter and the operation frequency has 166MHz-66MHz range.(at 2.5V, TYP. condition)

• Proceedings of the KSR Conference
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• 2011.05a
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• pp.1618-1628
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• 2011

The Train Diagnostic and Control System(TDCS) has been equipped on the modern Metro Vehicle, Locomotive and High Speed Train. The main purpose of this system is to support the identification of train status by real-time, the fast action against such failure events during revenue service and the fast convenient maintenance processes. Some of newest TCMS, a kind of control and monitoring system, has participated in the main control functions such as pantograph up and down, powering and braking command and so on. But these kind of control functions of the high speed train which has the operating speed over 300km/h are conducted by the train electrical logic circuits. The KTX-I and KTX-II - the local high speed train, are the typical example. The next generation TDCS for the ongoing project of distributed high speed train(HEMU) is designing with the target to increase main train control functions, to increase the reliability/avalibility and to increase the convenient driving. This paper introduces the overall configurations and functions of the new generation TDCS.