• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2009년도 추계학술대회 논문집
• /
• pp.23-24
• /
• 2009

• 대한전자공학회논문지SD
• /
• 제44권6호
• /
• pp.89-93
• /
• 2007

본 논문은 3.3V, $0.35{\mu}m$ CMOS 기술을 이용하여 I/O 인터페이스를 설계, 검증하였다. LVDS (low-voltage differential signaling)는 차동전송 방식과 저 전압의 스윙으로 저 전력 고속의 데이터를 전송할 수 있다. 본 논문은 기존의 차동증폭기나 감지 증폭기를 사용한 LVDS와 달리 telescopic 증폭기를 이용하여 2.3 Gbps의 빠른 전송속도를 갖는 LVDS 고속 인터페이스를 구현하였다. LVDS의 표준을 모두 충족하였고 25.5mW의 전력소모를 갖는다. 이 회로는 삼성 $0.35{\mu}m$ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
• /
• pp.2637-2640
• /
• 2003

In this paper, we propose a simple and efficient data input/output block with high speed between Motorola MPC8XX microprocessor and memory devices. Proposed method is capable of high speed data read and write using the address decoder and the burst cycle between Motorola PowerPC based MPC8XX microprocessor and fixed address locating memory devices such as FIFO, PCMCIA card, and so on. Experimental results are given our findings and discussions.

• 한국결정성장학회지
• /
• 제12권3호
• /
• pp.161-164
• /
• 2002

Polycrystalline and epitaxial heterostructure films of $La_{0.5}Sr_{0.5}CoO_{3}/Pb(Nb_{0.04}Zr_{0.28}Ti_{0.68})O_{3}/La_{0.5}Sr_{0.5}CoO_{3}$ (LSCO/PNZT/LSCO) capacitors were evaluated in terms of low voltage and high speed operation in high density memory, using TiN/Pt conducting barrier combination. Structural studies for a high density ferroelectric memory process flow, which requires the integration of conducting barrier layers to connect the drain of the pass-gate transistor to the bottom electrode of the ferroelectric stack, indicate complete phase purity (i.e. fully perovskite) in both epitaxial and polycrystalline materials. The polycrystalline capacitors show lower remnant polarization and coercive voltages. However, the retention, and high-speed characteristics are similar, indicating minimal influence of crystalline quality on the ferroelectric properties.

• 한국표면공학회지
• /
• 제35권3호
• /
• pp.127-132
• /
• 2002

High speed performance of ferroelectric Pb(Zr,Ti)$O_3$ (PZT) based capacitors is reported. La substitution up to 10% was performed to systematically lower the coercive and saturation voltages of epitaxial ferroelectric capacitors grown on Si using a ($Ti_{0.9}$ /$Al_{0.1}$ )N/Pt conducting barrier composite. Ferroelectric capacitors substituted with 10% La show significantly lower coercive voltage compared to capacitors with 0% and 3% La. This is attributed to a systematic decrease in the tetragonality (i.e., c/a ratio) of the ferroelectric phase. Furthermore, the samples doped with 10% La showed dramatically better retention and pulse width dependent polarization compared to the capacitors with 0% and 3% La. These capacitors show promise as storage elements in low power high density memory architectures.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.731-734
• /
• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

• 전자공학회논문지A
• /
• 제33A권12호
• /
• pp.110-119
• /
• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

• 전기전자학회논문지
• /
• 제10권2호통권19호
• /
• pp.141-148
• /
• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• Journal of electromagnetic engineering and science
• /
• 제4권2호
• /
• pp.56-62
• /
• 2004

We present a multi-Gbit/s digital I/O interface based on RF-modulation and capacitive-coupling over an impedance matched transmission line. The RF-interconnect(RFI) can greatly reduce the digital switching noise and eliminate the dc power dissipation over the channel. It also enables reduced signal amplitude(as low as 200 ㎷) with enhanced data rate and affordable circuit overhead. This paper addresses the system advantages and implementation issues of RFI. A prototype on-chip RFI transceiver is implemented in 0.18-${\mu}{\textrm}{m}$ CMOS. It demonstrates a maximum data rate of 2.2 Gbit/s via 10.5-㎓ RF-modulation. The RFI can be very instrumental for future high-speed inter- and intra-ULSI data links.

• 한국생산제조학회지
• /
• 제4권4호
• /
• pp.61-68
• /
• 1995

TiC-Al2O3 composite ceramics has high hardness, high strength, high wear and corrosion resistance. Therefore, composite ceramics have been concerned significantly with some excellent properties and many functions as new industrial materials to the industry at large. In present research, experiments are carried out to obtain the machinability and machining properties by EDM. As a result, the most suitable machining conditions of TiC-Al2O3 composite ceramics was that the pulse duration is 10-60$mutextrm{s}$, the peak current is 10-16A. The machining speed and the wear of the tool electrode increased with the increase in peak current.