• 전자공학회논문지B
• /
• 제30B권2호
• /
• pp.19-32
• /
• 1993

This paper suggests the new high-speed input/output techniques in a shared memory multiprocessor system. The high-speed I/O processor which can connect the different kinds of large sized I/O periperal devices, the communication protocol to the main processing units for I/O operations, and the job scheduling scheme are addressed. This paper also introduces the disk cache technique which supports the slow I/O devices comparing with the main processing units. These techniques were implemented in the TICOM system. The performance evaluation statistics were collected and analyzed for the suggested high-speed I/O processing techniques. These statistics show the superiority of the suggested techniques.

• 마이크로전자및패키징학회지
• /
• 제20권4호
• /
• pp.69-74
• /
• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• ETRI Journal
• /
• 제37권5호
• /
• pp.906-916
• /
• 2015

High-speed I/O channels require adaptive techniques to optimize the settings for filter tap weights at decision feedback equalization (DFE) read channels to compensate for channel inter-symbol interference (ISI) and crosstalk from multiple adjacent channels. Both ISI and crosstalk tend to vary with channel length, process, and temperature variations. Individually optimizing parameters such as those just mentioned leads to suboptimal solutions. We propose a joint optimization technique for crosstalk cancellation (XTC) at DFE to compensate for both ISI and XTC in high-speed I/O channels. The technique is used to compensate for between 15.7 dB and 19.7 dB of channel loss combined with a variety of crosstalk strengths from $60mV_{p-p}$ to $180mV_{p-p}$ adaptively, where the transmit non-return-to-zero signal amplitude is a constant $500mV_{p-p}$.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 하계학술대회 논문집 D
• /
• pp.2628-2630
• /
• 2004

In this study, a system that has a high speed digital data I/O and distributive structure is developed and the hardware and software of the system are described in detail. PCI master card to PC slot has maximum 63 slaves which are connected by Ethernet cables and can handle 16 I/O points. The system has some features : easy expansion by adding slaves as needed, space and wiring advantage with distributed characteristics, and select from a range of slave devices that fits best for the use.

• 대한기계학회:학술대회논문집
• /
• 대한기계학회 2007년도 춘계학술대회A
• /
• pp.951-956
• /
• 2007

This paper suggests a high-speed control method which is suitable for multi-joint robots using a real-time stand-alone controller for general-purpose. The fast processing controller consists of a PCI Interface Board and 2-axe PWM drivers. The PCI Interface Board consists of 32-channel PWM output ports, 32-channel Encoder Counters, 32-channel A/D Converters and 48-channel Digital I/O ports, and all the I/O data transmissions are completed within 1ms. And The 2-axe PWM driver can be redesigned easily in order to embed in each link. Experimental implementations show that the high-speed control method can be used for the real-time control which is essential to controlling of multi-body robots such as humanoid robots. Especially, it is efficient for realizing the model-based motion control in demand of much calculation time by the high I/O communication speed.

• 정보과학회 논문지
• /
• 제43권7호
• /
• pp.736-743
• /
• 2016

멀티코어 시스템에서 코어 친화도가 네트워크 I/O 성능에 미치는 영향은 다양한 연구들을 통해 관찰 되었다. 점차 고속화되는 네트워크 연결의 발전에 따라 효율적인 코어 친화도 정책은 중요한 성능 요소가 될 수 있다. 미들웨어 수준의 동적 코어 친화도 프레임워크는 네트워크와 디스크 I/O를 함께 고려한 코어 친화도 정책을 제안하였지만 다중 큐에 대한 고려는 이루어지지 않았다. 본 논문에서는 기존 동적 코어 친화도 프레임워크에 사용된 알고리즘을 다중 큐를 지원하기 위한 구조로 확장하고, 40 기가비트 이더넷과 NVMe 디바이스를 장착한 시스템에서 파일 업로드 성능을 분석한다. 실험 결과 다중 큐를 지원하기 위한 동적 코어 친화도는 하둡 분산 파일 시스템의 파일 업로드 처리량을 최대 32% 향상시켰으며 매니코어 시스템에서 더 나은 확장성을 제공할 수 있음을 확인하였다. 또한 다중 큐 조합에 따른 성능 영향에 대해 분석하여 다중 큐 분배 조합을 위해 고려해야 할 성능 요소들에 대해 논의한다.

• 한국산업정보학회논문지
• /
• 제18권2호
• /
• pp.27-34
• /
• 2013

대용량의 NAND 플래시 메모리가 출시됨으로써, 다양한 용도로 사용이 가능해 졌다. 특히 모바일기기의 멀티미디어 기능 확장으로 인해 대용량 NAND 플래시 메모리의 수요가 증가하고 있다. YAFFS2, NILFS2, JFFS2 파일시스템은 NAND 플래시 메모리 전용 파일시스템이다. 본 논문에서는 각 3개의 파일시스템에 4개의 I/O scheduler : CFQ(Complete Fair Queuing) I/O scheduler, NOOP(No Operation) I/O scheduler, Anticipatory I/O scheduler, Deadline I/O scheduler에 대한 순차적인 읽기, 쓰기 성능을 분석하였다. JFFS2 파일시스템 상에서의 Anticipatory I/O scheduler가 다른 I/O scheduler보다 쓰기 8%, 읽기 1.5% 이상 시간이 단축되었다. YAFFS2 파일시스템상에서는 4개의 I/O scheduler 시간이 일정하다. NILFS2 파일시스템에서는 Deadline I/O scheduler가 다른 I/O scheduler보다 쓰기 2%, NOOP I/O scheduler가 읽기 6%정도 시간이 단축 된다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
• /
• pp.345-348
• /
• 2000

In this paper, We described the procedures to generate an input-output buffer information specification (IBIS) model in digital IC circuits. We gives the method to describe IBIS standard I/O for the characteristics of I/O buffer and to represent its electrical characteristics. The parameters of I/O structure for I/O buffer modelling are also referred, and an IBIS model for CMOS, TTL IC, ROM and RAM constructed amounts about 216. This IBIS model can be used to the simulation of signal integrity of high speed circuits in a PCB level.

• 대한전기학회논문지:시스템및제어부문D
• /
• 제55권5호
• /
• pp.229-235
• /
• 2006

High speed PC-based DIO(Digital I/O) system that consists of a master device and slave I/O devices is developed. The PCI interfaced master device controls all of serial communications, reducing the load on the CPU to a minimum. The slave device is connected from the master device and another slave device is connected to the slave device, it can repeated to maximum 64 slave devices. The slave device has 3 types I/O mode, such as 16 bits input-only, 16 bits output-only, and 8bits input-output. The master device has 2 rings which can take 64 slaves each. Therefore, total I/O points covered by the master is 2048 points. The slave features 3 types of input/output function interchangeability by DIP switch settings. Library, application, and device driver software for the DIO system that have a secure and a convenient functionality are developed.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2009년도 춘계학술대회 논문집
• /
• pp.485-486
• /
• 2009