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Improved DC-DC Bidirectional Converter (개선된 DC-DC 양방향 컨버터)

  • Kim, Seong-Hwan;Hur, Jae-Jung;Jeong, Bum-Dong;Yoon, Kyoung-Kuk
    • Journal of Advanced Marine Engineering and Technology
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    • v.41 no.1
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    • pp.76-82
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    • 2017
  • Since the introduction of electronically controlled engines and electric propulsion ships, the need for an uninterruptible power supply for emergency power supply devices that use batteries has gained importance. The bidirectional converter in such emergency power supply devices is a crucial component. This paper proposes, a topology for an improved DC-DC bidirectional converter that is characterized by a high voltage conversion ratio and low voltage stress of switches. To confirm the performance of the converter, a computer simulation was executed with PSIM software. The conversion ratio of the proposed converter was found to be four times higher than the conventional boost converter in step-up mode and one-fourth that of the conventional buck converter in step-down mode, and the voltage stress of the switches was one-fourth of the high-side voltage. Moreover, the proposed converter was confirmed to be able to distribute equal currents between two interleaved modules without using any extra current-sharing control method because of the charge balance of its blocking capacitors.

Investigation of TaNx diffusion barrier properties using Plasma-Enhanced ALD for copper interconnection

  • Han, Dong-Seok;Mun, Dae-Yong;Gwon, Tae-Seok;Kim, Ung-Seon;Hwang, Chang-Muk;Park, Jong-Wan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.178-178
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    • 2010
  • With the scaling down of ULSI(Ultra Large Scale Integration) circuit of CMOS(Complementary Metal Oxide Semiconductor)based electronic devices, the electronic devices become more faster and smaller size that are promising field of semiconductor market. However, very narrow line width has some disadvantages. For example, because of narrow line width, deposition of conformal and thin barrier is difficult. Besides, proportion of barrier width is large, thus resistance is high. Conventional PVD(Physical Vapor Deposition) thin films are not able to gain a good quality and conformal layer. Hence, in order to get over these side effects, deposition of thin layer used of ALD(Atomic Layer Deposition) is important factor. Furthermore, it is essential that copper atomic diffusion into dielectric layer such as silicon oxide and hafnium oxide. If copper line is not surrounded by diffusion barrier, it cause the leakage current and devices degradation. There are some possible methods for improving the these secondary effects. In this study, TaNx, is used of Tertiarybutylimido tris (ethylamethlamino) tantalum (TBITEMAT), was deposited on the 24nm sized trench silicon oxide/silicon bi-layer substrate with good step coverage and high quality film using plasma enhanced atomic layer deposition (PEALD). And then copper was deposited on TaNx barrier using same deposition method. The thickness of TaNx was 4~5 nm. TaNx film was deposited the condition of under $300^{\circ}C$ and copper deposition temperature was under $120^{\circ}C$, and feeding time of TaNx and copper were 5 seconds and 5 seconds, relatively. Purge time of TaNx and copper films were 10 seconds and 6 seconds, relatively. XRD, TEM, AFM, I-V measurement(for testing leakage current and stability) were used to analyze this work. With this work, thin barrier layer(4~5nm) with deposited PEALD has good step coverage and good thermal stability. So the barrier properties of PEALD TaNx film are desirable for copper interconnection.

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A study on Improvement of sub 0.1$\mu\textrm{m}$VLSI CMOS device Ultra Thin Gate Oxide Quality Using Novel STI Structure (STI를 이용한 서브 0.1$\mu\textrm{m}$VLSI CMOS 소자에서의 초박막게이트산화막의 박막개선에 관한 연구)

  • 엄금용;오환술
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.9
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    • pp.729-734
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    • 2000
  • Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

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Design of Power IC Driver for AMOLED (AMOLED 용 Power IC Driver 설계)

  • Ra, Yoo-Chan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.19 no.5
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    • pp.587-592
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    • 2018
  • Because the brightness of an AMOLED is determined by the flowing current, each pixel of AMOLED operates via A current driving method. Therefore, it is necessary to supply power to adjust the amount of current according to THE user's requirement for AMOLED driving. In this study, an IP driver block was designed and a simulation was conducted for an AMOLED display, which supplies power as selected by users. The IP driver design focused on regulating the output power due to the OLED characteristics for the diode electric current according to the voltage to be activated by pulse-skipping mode (PSM) under low loads, and 1.5 MHz pulse-width modulation (PWM) for medium/high loads. The IP driver was designed to eliminate the ringing effects appearing from the dis-continue mode (DCM) of the step-up converter. The ringing effects destroy the power switch within the IC, or increase the EMI to the surrounding elements. The IP driver design minimized this through a ringing killer circuit. Mobile applications were considered to enable true shut-down capability by designing the standby current to fall below $1{\mu}A$ to disable it. The driver proposed in this paper can be applied effectively to the same system as the AMOLED display dual power management circuit.

High Efficiency H-Bridge Multilevel Inverter System Using Bidirectional Switches (양방향 스위치를 이용한 고효율 H-Bridge 멀티레벨 인버터 시스템)

  • Lee, Hwa-Chun;Hwang, Jung-Goo;Kim, Sun-Pil;Choi, Woo-Seok;Lee, Sang-Hyeok;Park, Seong-Mi;Park, Sung-Jun
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.28 no.10
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    • pp.16-26
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    • 2014
  • This paper proposes new 13-level inverter topology and DC/DC converter buck-boost structure topology for multilevel, compounding uni-directional and bi-directional switches, and proposes high-efficient multilevel inverter system in which the proposed two PCS(Power Conditioning System) was connected in series. In proposed multilevel inverter of forming a output 13-level phase voltage by using total 18 switching parts, Then bi-directional switch has a characteristic of reducing conduction loss and controlling the reactive power effectively by separating electrically from the neutral point. DC/DC converter for supplying in dependent 3 DC voltage to the proposed multi-level inverter generates 180-degree phase shifted PWM by the symmetrically combined structure of 2 buck-boost converter and twice switching frequency efficiency can be obtained, meanwhile, the converter can step up/down the output voltage and 20% output can be generated comparing the input voltage. This proposed system is verified with the simulation and laboratory test.

A Medium-Voltage Matrix Converter Topology for Wind Power Conversion with Medium Frequency Transformers

  • Gu, Chunyang;Krishnamoorthy, Harish S.;Enjeti, Prasad N.;Zheng, Zedong;Li, Yongdong
    • Journal of Power Electronics
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    • v.14 no.6
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    • pp.1166-1177
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    • 2014
  • A new type of topology with medium-frequency-transformer (MFT) isolation for medium voltage wind power generation systems is proposed in this paper. This type of converter is a high density power conversion system, with high performance features suitable for next generation wind power systems in either on-shore or off-shore applications. The proposed topology employs single-phase cascaded multi-level AC-AC converters on the grid side and three phase matrix converters on the generator side, which are interfaced by medium frequency transformers. This avoids DC-Link electrolytic capacitors and/or resonant L-C components in the power flow path thereby improving the power density and system reliability. Several configurations are given to fit different applications. The modulation and control strategy has been detailed. As two important part of the whole system, a novel single phase AC-AC converter topology with its reliable six-step switching technique and a novel symmetrical 11-segment modulation strategy for two stage matrix converter (TSMC) is proposed at the special situation of medium frequency chopping. The validity of the proposed concept has been verified by simulation results and experiment waveforms from a scaled down laboratory prototype.

Process-Variation-Adaptive Charge Pump Circuit using NEM (Nano-Electro-Mechanical) Relays for Low Power Consumption and High Power Efficiency

  • Byeon, Sangdon;Shin, Sanghak;Song, Jae-Sang;Truong, Son Ngoc;Mo, Hyun-Sun;Lee, Seongsoo;Min, Kyeong-Sik
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.5
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    • pp.563-569
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    • 2015
  • For some low-frequency applications such as power-related circuits, NEM relays have been known to show better performance than MOSFETs. For example, in a step-down charge pump circuit, the NEM relays showed much smaller layout area and better energy efficiency than MOSFETs. However, severe process variations of NEM relays hinder them from being widely used in various low-frequency applications. To mitigate the process-variation problems of NEM relays, in this paper, a new NEM-relay charge pump circuit with the self-adjustment is proposed. By self-adjusting a pulse amplitude voltage according to process variations, the power consumption can be saved by 4.6%, compared to the conventional scheme without the self-adjustment. This power saving can also be helpful in improving the power efficiency of the proposed scheme. From the circuit simulation of NEM-relay charge pump circuit, the efficiency of the proposed scheme is improved better by 4.1% than the conventional.

Analysis and Control of a Modular MV-to-LV Rectifier based on a Cascaded Multilevel Converter

  • Iman-Eini, Hossein;Farhangi, Shahrokh;Khakbazan-Fard, Mahboubeh;Schanen, Jean-Luc
    • Journal of Power Electronics
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    • v.9 no.2
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    • pp.133-145
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    • 2009
  • In this paper a modular high performance MV-to-LV rectifier based on a cascaded H-bridge rectifier is presented. The proposed rectifier can directly connect to the medium voltage levels and provide a low-voltage and highly-stable DC interface with the consumer applications. The input stage eliminates the necessity for heavy and bulky step-down transformers. It corrects the input power factor and maintains the voltage balance among the individual DC buses. The second stage includes the high frequency parallel-output DC/DC converters which prepares the galvanic isolation, regulates the output voltage, and attenuates the low frequency voltage ripple ($2f_{line}$) generated by the first stage. The parallel-output converters can work in interleaving mode and the active load-current sharing technique is utilized to balance the load power among them. The detailed analysis for modeling and control of the proposed structure is presented. The validity and performance of the proposed topology is verified by simulation and experimental results.

Turnaround of Korean IT Venture firms by u-Korea (u-Korea를 통한 한국 IT벤처의 활성화 방안)

  • Hwang Doo-Hee;Lee Jong-Min;Chung Sun-Yang
    • Proceedings of the Korea Technology Innovation Society Conference
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    • 2005.05a
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    • pp.46-59
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    • 2005
  • After the IMF jurisdiction period, the Korean economy experienced a venture boom. Korean venture enterprises had been recognized that high profitable and high technology capacity based. These ventures also have contributed to national added value tolerably. In particular, Korean information technology (IT) venture companies got away the order of economy concentrated big companies, which were taken the opportunity of new economy to make suggestion of the future courses and to open an e-Korea era. However, IT ventures firms or dotcom enterprises have had difficulties through sinking down their bubbles and slumping technology sector from the first half of the 2000. In consideration of Korea IT venture companies' conditions, Korean government introduce new national vision in order to go ahead of intelligence based society form knowledge based. Korea is planning new investment to meet with the challenge of globalization proactively by national band named u-Korea. As following a step in IT infrastructure, it will give Korean IT ventures new demand creative technologies and services by new technological windows of opportunity. This situation is expected that will become an economic take-off. This paper will look for the way to stimulate Korean IT ventures' competence and present new frontier of IT ventures turnaround.

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Influence of Thermal Cycle Test of a 22.9 kV High Temperature Superconducting Cable System (22.9 kV 초전도케이블 시스템의 Thermal Cycle Test 영향)

  • Sohn, S.H.;Lim, J.H.;Yang, H.S.;Ryoo, H.S.;Choi, H.O.;Sung, T.H.;Kim, D.L.;Hwang, S.D.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.11a
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    • pp.242-242
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    • 2007
  • To verify the applicability of High Temperature Superconducting (HTS) cable system into the real grid, the HTS cable system with the specification of 22.9 kV, 1250 A, 100 m long was installed in the second quarter of 2006, and the long term field test has been in progress at the KEPCO's Gochang power testing yard. Apart from the conventional power cable, HTS cable system requires sufficient thermo-mechanical strength to endure a large temperature difference. To date, the KEPCO HTS cable system was cooled down and warmed to the room temperature several times to investigate the influence of thermal cycles experimentally. Dielectric properties, critical current dependance and heat losses were evaluated at each step of thermal cycle. The test results showed that thermal cycle did not induce the degradation of dielectric properties, and the critical current decreased to 5 % of the initial value.

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