• Proceedings of the KSR Conference
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• 2008.11b
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• pp.321-324
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• 2008

Recently, there is an increasing demand for efficient high power/weight auxiliary power supplies for use on high speed traction application. many new conversion techniques have been proposed to reduce the voltage and current stress of switching components, and the switching losses in the traditional pulse width modulation(PWM) converter. Among them, the phase shift full bridge zero voltage switching PWM techniques are thought most desirable for many applications because this topology permits all switching devices to operate under zero voltage switching(ZVS) by using circuit parasitic components such as leakage inductance of high frequency transformer and power device junction capacitance. The proposed topology is found to have higher efficiency than conventional soft-switching converter. Also it is easily applicable to phase shift full bridge converter by applying an energy recovery snubber consisted of fast recovery diodes and capacitors.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.233-233
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• 2000

Direct torque control (DTC) scheme provides a very quick torque response without the complex field-orientation block and inner current regulation loop. DTC is known as an appropriate scheme for high power induction motet drives because it can be used at lower switching frequency. There are two major drawbacks with the application of DTC schemes : one is large current harmonics due to flux drooping in a low speed range, the other is that the inverter switching frequency is varying according to motor parameters and operating speed. Switching devices in the power electronics drives should be supported for relatively high switching frequency. In this paper, a P-type fuzzy controller to realize the variable switching sector scheme and a PID-type fuzzy switching frequency regulator are adopted. A meaningful contribution of this paper is to propose a simple realization scheme of the fuzzy switching frequency regulator. Simulation results show the effectiveness of those propositions.

• ETRI Journal
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• v.38 no.1
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.152.1-152
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• 2001

This paper presents a high performance and cost effective way by using an FPGA circuit to implement torque controller so that the SRM can operate at high speed. In order to increase the operating speed, we need to implement both the torque and the current controllers by using an FPGA. However, it is difficult to implement all of the torque controller in the FPGA. Moreover, implementation of a time critical part is sufficient for improving the performance. One of the time critical part is the switching angle control. In this study, torque controller which calculate the switching on and commutation angles is implemented in PC because these angle are a function of rotor velocity which is varied slowly, and switching angle controller ...

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.352-352
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• 2010

Silicon Carbide (SiC) power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this paper, we report the effect of the P-base doping concentration ($N_{PBASE}$) on the transient characteristics of 4H-SiC DMOSFETs. By reducing $N_{PBASE}$, switching time also decreases, primarily due to the lowered channel resistance. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimization of superior switching performance.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1133-1135
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• 1992

This paper describes high frequency inverter using zero voltage switching(ZVS). The ZVS operation is achieved to reduce the switching stress and switching loss under high speed switching. The proposed circuit configuration and performance are discussed. Its operation characteristics are evaluated through computer-aided simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.809-815
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• 2003

It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1255-1267
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• 2018

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.167-173
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• 2005

The isolation of the series PIN diode switch is restricted by the parallel capacitance of PIN diode and the switch driver circuit limits switching speed of PIN diode switch. To overcome these problems, a high isolation and high switching speed Pin diode switch is proposed adapting the parallel resonant inductance and TTL compatible switch driver circuit. The measurement results of the 3 GHz PM diode switch show 1 GHz frequency band, less than 1.5 dB insertion loss, 65 dB isolation, more than 15 dB return loss and less than 30 ns switching speed. In particular the 3 GHz PIN diode switch using the parallel resonant inductance exhibits the improvement of isolation by 15 dB.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.11a
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• pp.33-36
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• 1999

In this paper, we proposed a simultaneous switching noise(SSN) reduction technique in muti-layer beards(MLB) for high-speed digital applications and analyzed them using the Finite Difference Time Domain(FDTD) method. The new method by conductive dielectric substrates reduces SSN couplings and resonances, significantly, which cause series malfunctions in the modem high-speed digital applications.