• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.11a
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• pp.377.2-377
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• 2002

In optical disk drives (ODD), the demands of high data density and high speed have been increasing rapidly to achieve high data capacity and data transfer rate The use of short wavelength laser and high track following performance are needed to raise data density and data rate. For high-performance actuator, the improvement of linearity and acceleration become more important. (omitted)

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.34-41
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• 1998

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.53-54
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• 2007

As Cable Network is developing for 2-way high speed data service, it should be developed to transfer high speed data using limited bandwidth. If QAM is using for this, synchronization algorithms become important system parameters. In this paper, we present two methods of coarse timing recovery using CAZAC sequence for cable modem uplink.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.444-447
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• 2004

A heart diagnosis system adopts hundreds of Superconducting Quantum Interface Device(SQUID) sensors for precision MCG(Magnetocardiogram) or MEG(Magnetoencephalogram) signal acquisitions. This system requires correct and real-time data acquisition from the sensors in a required sampling interval, i.e., 1 mili-second. This paper presents our hardware design and test results, to acquire data from 256 channel analog signal with 1-ksample/sec speed, using 12-bit 8-channel ADC devices, SPI interfaces, parallel interfaces, and 8-bit microprocessors. We chose to implement parallel data transfer between microprocessors as an effective way of achieving such data collection. Our result concludes that the data collection can be done in 250 ${\mu}sec$ time-interval.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.74-86
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• 2002

This paper proposes a VLSI architecture for high-speed data processing of the differential phase detectors with the decision feedback. To improve the BER performance of the conventional differential phase detection, DF-DPD, DPD-RGPR and DFDPD-SA have been proposed. These detection methods have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, the VLSI architecture was proposed for high-speed data processing of the differential phase detectors with decision feedback. The Proposed architecture has the pre-calculation method to previously calculate the results on 'N'th step at 'M-1'th step and the pre-decision feedback method to previously feedback the predicted phases at 'M-1'th step. The architecture proposed in this paper was implemented to RTL using VHDL. The simulation results show that the Proposed architecture obtains the high-speed data processing.

• Journal of Applied Reliability
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• v.1 no.2
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• pp.121-138
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• 2001

Due to large demand for high speed and great capacity for data transfer, WDM, which uses the wavelength division multiplexing technique, is known as alternative way to satisfy those demand for its flexible network operation and management, easy network expansion with existing networks, and enhancement of efficient data transfer rate. For these reasons, a new high capacity WDM optical communication network plan was established. Therefore, the quality of currently deployed optical cables with 81.6 km in length should be assessed to ensure if high capacity WDM system could be implemented on existing optical cables. Two important characteristic parameters, Transfer Loss and PMD (Polarization Mode Dispersion), were measured to evaluate quality of existing optical cable. Transfer Loss was measured at 0.244 dB per kilometer, which is lower than the design standard value at 0.275 dB/km. The measured PMD value gave at 0.030ps/km, and it, therefore, satisfies the value recommended by ITU-T (International Telecommunication Union-T) of 0.5ps/km. In addition, the transfer characteristic for existing 2.5 Gbps and 10 Gbps system were measured and evaluated, and the results showed that error-free transfer is very much feasible. Computer simulation for DWDM system, which is likely be a future backbone network in Korea, to assess the transfer characteristic using the same condition employed for 2.5 Gbps and 10 Gbps was carried out as well. The simulation verified that a stable network operation and reliable service could be provided.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.7
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• pp.539-546
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• 2002

This paper presents a new direct seek control scheme that provides fast data access capability and robust performance for high-speed rotational optical disk drives (ODD). When a disk is rotating at a high speed to obtain fast data transfer in ODD, the magnitude and frequency of velocity disturbance caused by eccentric rotation of the disk increase in proportion to the rotational speed of the disk. Such disturbances make it almost impossible for the conventional seek control scheme to achieve stable and satisfactory seek performance. We analyze the problems that may arise when the conventional seek control scheme is applied to the high-speed rotational ODD and propose a new direct seek control scheme that will solve such problems. In the proposed scheme, a seek control system is designed such that its performance is guaranteed for a set of plants with parameter perturbations. The performance of the proposed seek control scheme is shown by experiments using a high-speed rotational ODD.

• Investigative Magnetic Resonance Imaging
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• v.25 no.1
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• pp.10-22
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• 2021

Purpose: To overcome the difficulty in building a large data set with a high-quality in medical imaging, a concept of 'blended-transfer learning' (BTL) using a combination of both source data and target data is proposed for the target task. Materials and Methods: Source and target tasks were defined as training of the source and target networks to reconstruct cardiac CINE images from undersampled data, respectively. In transfer learning (TL), the entire neural network (NN) or some parts of the NN after conducting a source task using an open data set was adopted in the target network as the initial network to improve the learning speed and the performance of the target task. Using BTL, an NN effectively learned the target data while preserving knowledge from the source data to the maximum extent possible. The ratio of the source data to the target data was reduced stepwise from 1 in the initial stage to 0 in the final stage. Results: NN that performed BTL showed an improved performance compared to those that performed TL or standalone learning (SL). Generalization of NN was also better achieved. The learning curve was evaluated using normalized mean square error (NMSE) of reconstructed images for both target data and source data. BTL reduced the learning time by 1.25 to 100 times and provided better image quality. Its NMSE was 3% to 8% lower than with SL. Conclusion: The NN that performed the proposed BTL showed the best performance in terms of learning speed and learning curve. It also showed the highest reconstructed-image quality with the lowest NMSE for the test data set. Thus, BTL is an effective way of learning for NNs in the medical-imaging domain where both quality and quantity of data are always limited.

• Journal of the Korea Society of Computer and Information
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• v.25 no.7
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• pp.1-8
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• 2020

In this paper, we present an implementation of high speed image data transfer using XDMA for a video signal generation / acquisition device developed as a military test equipment. The technology proposed in this study obtains efficiency by replacing the method of copying data using the system buffer in the kernel area with the transmission and reception through the DMA engine in the FPGA. For this study, the device was developed as a PXIe platform in consideration of life cycle, and performance was maximized by using a low-cost FPGA considering mass productivity. The video I/O board implemented in this paper was tested by changing the AXI interface clock frequency and link speed through the existing memory copy method. In addition, the board was constructed using the DMA engine of the FPGA, and as a result, it was confirmed that the transfer speed was increased from 5~8Hz to 140Hz. The proposed method will contribute to strengthening defense capability by reducing the cost of device development using the PXIe platform and increasing the technology level.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.