• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.1
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• pp.1-10
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• 2004

This paper presents a navigation garde capacitive microaccelerometer, whose low-noise high-resolution detection capability is achieved by a new electrode design based on a high-amplitude anti-phase sense voltage. We reduce the mechanical noise of the microaccelerometer to the level of 5.5$\mu\textrm{g}$/(equation omitted) by increasing the proof-mass based on deep RIE process of an SOI wafer. We reduce the electrical noise as low as 0.6$\mu\textrm{g}$/(equation omitted) by using an anti-phase high-amplitude square-wave sense voltage of 19V. The nonlinearity problem caused by the high-amplitude sense voltage is solved by a new electrode design of branched finger type. Combined use of the branched finger electrode and high-amplitude sense voltage generates self force-balancing effects, resulting in an 140％ increase of the bandwidth from 726㎐ to 1,734㎐. For a fixed sense voltage of 10V, the total noise is measured as 2.6$\mu\textrm{g}$/(equation omitted) at the air pressure of 3.9torr, which is the 51％ of the total noise of 5.1$\mu\textrm{g}$/(equation omitted) at the atmospheric pressure. From the excitation test using 1g, 10㎐ sinusoidal acceleration, the signal-to-noise ratio of the fabricated microaccelerometer is measured as 105㏈, which is equivalent to the noise level of 5.7$\mu\textrm{g}$/(equation omitted). The sensitivity and linearity of the branched finger capacitive microaccelerometer are measured as 0.638V/g and 0.044％, respectively.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.469-478
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• 1994

In this paper, a high speed, high resolution information processing digital- analog converter was designed for high definition color graphic, digital image signal processing, HDTV. For high speed operation, matrix type current cell array, latch which is not use pipelined, and two dimensional structure decoder using transmission gate were designed. It is adopted to fast-conversion, low-power implementation and exhibited high performance at linearity and accuracy. To reduce silicon area and to maintain resolution, current cell array composed of weighted and non-weighted current cells. In this paper, deglitching current cell design for high accuracy, new switching algorithm assert to reduce switching error. It's This circuit dissipates 130W with a 5-V power supply, and operate above 100MHz with 10 bit resolution.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.2
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• pp.129-136
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• 2005

This paper presents a design strategy of SPOKE type BLDC motors considering an irreversible demagnetization of a permanent magnet (PM). So the irreversible demagnetization characteristic of the motor is analyzed by rotor structure. The instantaneous currents in either starting or lock rotor condition, which are calculated from the current dynamic analysis, are applied to the analysis of the irreversible demagnetization field by FEM. In irreversible demagnetization analysis by FEM, the variation of residual flux density in PM is analyzed using the non-linearity of magnetic core on B-H plan. The analysis results are compared to several rotor structures and used for optimize the rotor structure.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2083-2086
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• 2004

Variable Structure Controller with effective tracking performance is propose to control micro actuator system. Propsed VSC(Variable Structure Control) technique is implemented to tracking control of comb driving system having high non-linearity. The tracking performance due to VSC technique is compared to conventional PD(Proportional Derivative) control technique, reveals improved results.

• Proceedings of the KSR Conference
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• 2011.10a
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• pp.275-280
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• 2011

Due to high-speed of trains, the track deformation increases rapidly and may lead to track irregularities causing the track stability problem. To secure the track stability, the continual inspection on track irregularities is required. The paper presents a methodology for identifying track irregularity using the NARX neural network considering non-linearity in the train structural system. A simulation study has been carried out to examine the proposed method. Acceleration time history data measured at a bogie were re-sampled to every 0.25m track irregularity. In the simulation study, two sets of measured data were simulated. The second data set was obtained by a train with 10% more mass than the one for the first data set. The first set of simulated data was used to train the series-parallel mode of NARX neural network. Then, the track irregularities at the second time period are identified by using the measured acceleration data. The closeness of the identified track irregularity to the actual one is evaluated by PSD and RMSE.

• Journal of the Ergonomics Society of Korea
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• v.13 no.1
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• pp.59-74
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• 1994

The purposes of this paper were to suggest the procedures for a sizing sys- tem which can provide good fitting of apparel and minimize the loss due to excessive inventory, and to determine an adequate apparel sizing standard. An anthropometric database used for this study was the 1992 National Anthro- pometric Survey of Koreans. The database was limited to 1,336 women who were 18-51 years old. They study was conducted by classifying ages into two groups (18-33, 34-51) using Wilk's lamda. Three principal components : laterality( fullness), linearity(length) and characteristic of torso were selected to describe body types, and these three body type classification of each group were selected by cluster analysis. It was found that all intervals between standard sizes were not equal. They were narrow around the center with high frequencies of the customers but wide in both tail with low frequencies. It was also found that the optimal sizes suing the loss function can be applied well in practice.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1147-1152
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• 2004

Switched Reluctance Motors have an inexpensive, intrinsic simplicity and low cost that makes them well suited to home appliance and office applications. However the motor suffering with necessity of shaft position sensor, lead to non-linearity of operations. Further, the involvement of static converters deteriorates the operational power factor. Implementation of a sensorless algorithm, can remove the need of position sensors. Also, the drive includes a compact power factor control in the input stage by implementing Zero Current Switching Quasi-Resonant Boost Technology. This paper presented, aims at optimized low line current distortion, high power factor, low cost and a shaft position sensorless Switched Reluctance Motor drive.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1836-1840
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• 2003

This paper, we propose a new phase-locked loop (PLL) system with the controllable output phase, independent from the output frequency, and lock-up time. This PLL system has a dual control loop is described, the inner loop greatly improved VCO characteristic such as faster speed response as well as higher operation bandwidth, to minimize the effect of the VCO noise and the power supply variation and also get better linearity of VCO output. The main loop is the heart of this PLL which greatly improved the output frequency instability due to the external high frequency noise coupling to the input reference frequency also the main loop can control the output phase, independent from the output frequency, and reduce the lock-up time of the step frequency response. The experimental results confirm the validity of the proposed strategy.

• International Journal of Control, Automation, and Systems
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• v.5 no.6
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• pp.652-662
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• 2007

This paper presents a new and simple method for sensorless operation of matrix converter drives using a constant air-gap flux and the imaginary power flowing to the motor. To improve low-speed sensorless performance, the non-linearities of a matrix converter drive such as commutation delays, turn-on and turn-off times of switching devices, and on-state switching device voltage drop are modeled using PQR transformation and compensated using a reference current control scheme. The proposed compensation method is applied for high performance induction motor drives using a 3 kW matrix converter system. Experimental results are shown to illustrate the feasibility of the proposed strategy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.411-417
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• 2012

A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in $0.18{\mu}m$ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ps with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ps.