• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.463-464
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• 2006

This paper present experimental results by non-contact mode Atomic Force Microscopy using high aspect ratio tips (HAR-T). We fabricated the carbon nanotube tip based on dielectrophoresis and the carbon nano probe by focused ion beam after dielectrophoretic assembling. In this paper, we measure AAO sample and trench structure to estimate HAR-T's performance and compared with conventional Si tip. We confirmed that results of HAR-T's performance in non contact mode was very superior than conventional tip.

• 한국표면공학회지
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• 제57권3호
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• pp.165-178
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• 2024

In semiconductor memory device manufacturing, the capability for high aspect ratio contact (HARC) etching determines the density of memory device. Given that there is no standardized definition of "high" in high aspect ratio, it is crucial to continuously monitor recent technology trends to address technological gaps. Not only semiconductor memory manufacturing companies such as Samsung Electronics, SK Hynix, and Micron but also semiconductor manufacturing equipment companies such as Lam Research, Applied Materials, Tokyo Electron, and SEMES release annual reports on HARC etching technology. Although there is a gap in technological focus between semiconductor mass production environments and various research institutes, the results from these institutes significantly contribute by demonstrating fundamental mechanisms with empirical evidence, often in collaboration with industry researchers. This paper reviews recent studies on HARC etching and the study of dielectric etching in various technologies.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.563-564
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• 2008

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.136.2-136.2
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• 2015

반도체 제조는 chip의 성능 향상 및 단가 하락을 위해 지속적으로 pattern size가 nano size로 감소해 왔고, capacitor 용량은 증가해 왔다. 이러한 현상은 contact hole의 aspect ratio를 지속적으로 증가시킨바, 그에 따라 최적의 HARC (high aspect ratio contact)을 확보하는 적합한 dry etch process가 필수적이다. 그러나 HARC dry etch process는 많은 critical plasma properties 에 의존하는 매우 복잡한 공정이다. 따라서, critical plasma properties를 적절히 조절하여 higher aspect ratio, higher etch selectivity, tighter critical dimension control, lower P2ID과 같은 plasma characteristics을 확보하는 것이 요구된다. 현재 critical plasma properties를 제어하기 위해 다양한 plasma etching 방법이 연구 되어왔다. 이 중 plasma를 낮은 kHz의 frequency에서 on/off 하는 pulsed plasma etching technique은 nanoscale semiconductor material의 etch 특성을 효과적으로 향상 시킬 수 있다. 따라서 본 실험에서는 dual-frequency capacitive coupled plasma (DF-CCP)을 사용하여 plasma operation 동안 duty ratio와 pulse frequency와 같은 pulse parameters를 적용하여 plasma의 특성을 각각 제어함으로써 etch selectivity와 uniformity를 향상 시키고자 하였다. Selective SiO2 contact etching을 위해 top electrode에는 60 MHz pulsed RF source power를, bottom electrode에는 2MHz pulse plasma를 인가하여 synchronously pulsed dual-frequency capacitive coupled plasma (DF-CCP)에서의 plasma 특성과 dual pulsed plasma의 sync. pulsing duty ratio의 영향에 따른 etching 특성 등을 연구 진행하였다. 또한 emissive probe를 통해 전자온도, OES를 통한 radical 분석으로 critical Plasma properties를 분석하였고 SEM을 통한 etch 특성분석과 XPS를 통한 표면분석도 함께 진행하였다. 그 결과 60%의 source duty percentage와 50%의 bias duty percentage에서 가장 향상된 etch 특성을 얻을 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.666-670
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• 2004

VLSI 소자에서 design rule(D/R)이 작아져 각 단위 Pattern의 size가 작아짐에 따라 aspect ratio가 커지게 되었다. 산화막 contact etch를 하는데 있어 산화막 측벽을 보호하는데, 이러한 보호막은 주로 fluoro-carbon 계열의 polymer precursor들이 사용된다. Aspect ratio(A/R)가 5 이하일 때에는 측벽의 보호막에 의한 바닥 변형이 문제가 되지 않으나, 10 이상의 A/R를 가진 contact에서는 크기가 줄고, 모양이 불균형하게 변하는 바닥 변형을 쉴게 관찰할 수 있다. 이러한 바닥 변형이 커지면 contact 저항이 높아지는 것은 물론이고, 심하게는 하부 pattern과 overlap 불량을 유발할 수 있다. 본 논문에서는 바닥변형을 일으키는 원인을 분석하고 fluoro-carbon 계열의 polymer precursor의 종류$(C_4_F6\;vs.\;C_3F_8)$에 따른 polymer증착 상태 확인 및 pattern비대칭에 따른 바닥 변형의 고찰과 plasma etching 시 H/W 변형을 통해 바닥 변형이 거의 없는 조건을 찾아낼 수 있었다.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.389-395
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• 2005

The etching technology of the high aspect ratio contact(HARC) is necessary at the critical contact processes of semiconductor devices. Etching the $SiO_{2}$ contact hole with the sub-micron design rule in manufacturing VLSI devices, the unexpected phenomenon of 'profile tilting' or 'bottom distortion' is often observed. This makes a short circuit between neighboring contact holes, which causes to drop seriously the device yield. As the aspect ratio of contact holes increases, the high C/F ratio gases, $C_{4}F_{6}$, $C_{4}F_{8}$ and $C_{5}F_{8}$, become widely used in order to minimize the mask layer loss during the etching process. These gases provide abundant fluorocarbon polymer as well as high selectivity to the mask layer, and the polymer with high sticking yield accumulates at the top-wall of the contact hole. During the etch process, many electrons are accumulated around the asymmetric hole mouth to distort the electric field, and this distorts the ion trajectory arriving at the hole bottom. These ions with the distorted trajectory induce the deformation of the hole bottom, which is called 'profile tilting' or 'bottom distortion'. To prevent this phenomenon, three methods are suggested here. 1) Using lower C/F ratio gases, $CF_{4}$ or $C_{3}F_{8}$, the amount of the Polymer at the hole mouth is reduced to minimize the asymmetry of the hole top. 2) The number of the neighboring holes with equal distance is maximized to get the more symmetry of the oxygen distribution around the hole. 3) The dual frequency plasma source is used to release the excessive charge build-up at the hole mouth. From the suggested methods, we have obtained the nearly circular hole bottom, which Implies that the ion trajectory Incident on the hole bottom is symmetry.

• 한국가시화정보학회지
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• 제5권1호
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• pp.3-8
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• 2007

We present simple methods for fabricating high aspect-ratio polymer nanostructures on a solid substrate by rigiflex lithography with tailored capillarity and adhesive force. In the first method, a thin, thermoplastic polymer film was prepared by spin coating on a substrate and the temperature was raised above the polymer's glass transition temperature ($T_g$) while in conformal contact with a poly(urethane acrylate) (PUA) mold having nano-cavities. Consequently, capillarity forces the polymer film to rise into the void space of the mold, resulting in nanostructures with an aspect ratio of ${\sim}4$. In the second method, very high aspect-ratio (>20) nanohairs were fabricated by elongating the pre-formed nanostructures upon removal of the mold with the aid of tailored capillarity and adhesive force at the mold/polymer interface. Finally, these two methods were further used to fabricate micro/nano hierarchical structures by sequential application of the molding process for mimicking nature's functional surfaces such as a lotus leaf and gecko foot hairs.

• Journal of Welding and Joining
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• 제8권1호
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• pp.62-69
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• 1990

Being focused on the recent studies that the fatigue strength of resistance spot weldmentes can be improved by using ellipsoidal weld nuggets, the voltage and temperature distribution in resistance spot weldments were simulated for the various rectangular electrodes which had the different aspect ratio of the contact area. Because the electrode shape was not axi-symmetric, the solution domain for simulation should be three dimensional. A series of experiments were carred out to verify the analytically obtained temperature distribution in the weldment. From the calculational and experimental results, it could be revealed that the nugget took the form of ellipsoid, while both results showed a considerable discrepancy for the high aspect ratio.

• Tribology and Lubricants
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• 제18권3호
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• pp.228-234
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• 2002

Generally, space structures are subjected to severe situations, such as, sublimation, strong evaporation of lubricants, thermal stresses, high temperature gradients, irradiation, impacts by microscopic meteorites, and other factors. Recent]y, various kinds of coatings are applied to the parts under heavy contact stresses, in order to insure long wear-free lives and/or reduce friction coefficients. In space structures, molybdenum disulfide is using frequently. Moreover TiN, Al$_2$O$_3$, PTFE(Poly Tetra Fluor Ethylene) are introduced recently for space structure. In this part we are going to apply the partial model method, developed in reference[11] to analyze part with coated layer. In referencer[l1], we compute the reasonable size of partial model and aspect ratio. Using these data, we analyze the structures coated with TiN, Al$_2$O$_3$, PTFE under contact load, temperature and crack model . Beside, we consider the stress analysis under time dependent load and transient thermal effect.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2004년도 제27회 학술발표회 초록집
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• pp.75-75
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• 2004