• Title/Summary/Keyword: hardware testbed

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Development of Open IoT platform based on Open Source Hardware & Cloud Service (오픈소스 하드웨어와 클라우드 서비스 기반의 개방형 IoT 플랫폼 구축)

  • Ryu, Dae-Hyun;Choi, Tae-Wan
    • The Journal of the Korea institute of electronic communication sciences
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    • v.11 no.5
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    • pp.485-490
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    • 2016
  • The era of IoT in which all objects are intelligent and are connected to the internet has been started. In order to establish and activate an IoT eco system, open IoT services platform is very important. In this paper, we develop an open IoT services platform and verified the function by building a testbed. Our platform based on the open source hardware and commercial cloud services such as AWS which is a component of an open service IoT platform.

Performance Analysis of Processors for Next Generation Satellites (차세대 위성 프로세서 선정을 위한 성능 분석)

  • Yoo, Bum-Soo;Choi, Jong-Wook;Jeong, Jae-Yeop;Kim, Sun-Wook
    • IEMEK Journal of Embedded Systems and Applications
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    • v.14 no.1
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    • pp.51-61
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    • 2019
  • There are strict evaluation processes before using new processors to satellites. Engineers evaluate processors from various viewpoints including specification, development environment, and cost. From a viewpoint of computation power, manufacturers provide benchmark results with processors, and engineers decide which processors are adequate to their satellites by comparing the benchmark results with requirements of their satellites. However, the benchmark results depends on a test environment of manufacturers, and it is quite difficult to achieve similar performance in a target environment. Therefore, it is necessary to evaluate the processors in the target environment. This paper compares performance of a processor, AT697F/LEON2, in software testbed (STB) with three development boards of XC2V/LEON3, GR712RC/LEON3, and GR740/LEON4. Seven benchmark functions of Dhrystone, Stanford, Coremark, Whetstone, Flops, NBench, and MiBench are selected. Results are analyzed with hardware and software properties: hardware properties of core architecture, number of cores, cache, and memory; and software properties of build options and compilers. Based on the analysis, this paper describes a guideline for choosing processors for next generation satellites.

Design and Verification of Spacecraft Pose Estimation Algorithm using Deep Learning

  • Shinhye Moon;Sang-Young Park;Seunggwon Jeon;Dae-Eun Kang
    • Journal of Astronomy and Space Sciences
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    • v.41 no.2
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    • pp.61-78
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    • 2024
  • This study developed a real-time spacecraft pose estimation algorithm that combined a deep learning model and the least-squares method. Pose estimation in space is crucial for automatic rendezvous docking and inter-spacecraft communication. Owing to the difficulty in training deep learning models in space, we showed that actual experimental results could be predicted through software simulations on the ground. We integrated deep learning with nonlinear least squares (NLS) to predict the pose from a single spacecraft image in real time. We constructed a virtual environment capable of mass-producing synthetic images to train a deep learning model. This study proposed a method for training a deep learning model using pure synthetic images. Further, a visual-based real-time estimation system suitable for use in a flight testbed was constructed. Consequently, it was verified that the hardware experimental results could be predicted from software simulations with the same environment and relative distance. This study showed that a deep learning model trained using only synthetic images can be sufficiently applied to real images. Thus, this study proposed a real-time pose estimation software for automatic docking and demonstrated that the method constructed with only synthetic data was applicable in space.

A Development of Real-time Monitoring Techniques for Synchronous Electric Generator Systems (동기 발전기 시스템의 실시간 모니터링 기술 개발)

  • Cho, Hyun Cheol
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.66 no.4
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    • pp.182-187
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    • 2017
  • Synchronous generators have been significantly applied in large-scale power plants and its monitoring systems are additionally established to sequentially observe states and outputs. We develop a computer based monitoring device for three-phase synchronous power generators in this paper. First, a test-bed of such generator system is created and then a interface board is constructed to transfer electric signals including the output voltage and the current from generators into a computer system via a data acquisition device. Its RMS(root-mean-square) values are continuously shown on a screen of computer systems and its time-histories graphs are additionally illustrated under a graphic user interface(GUI) mode. Lastly, we carry out real-time experiments using the generator system with the monitoring device to demonstrate its reliability and superiority by comparing results of a generic power analyzer which is well-used in measuring various power systems practically.

Control validation of Peugeot 3∞8 HYbrid4 Vehicle Using a Reduced-scale Power HIL Simulation

  • Letrouve, Tony;Lhomme, Walter;Bouscayrol, Alain;Dollinger, Nicolas
    • Journal of Electrical Engineering and Technology
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    • v.8 no.5
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    • pp.1227-1233
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    • 2013
  • The new engineering challenges lead to a control of a vehicle more and more complex. To tackle this issue, Hardware-In-the-Loop (HIL) simulation is used in the development of real-time embedded systems. In this paper, the control of a double parallel hybrid vehicle is validated using a reduced power HIL simulation. A graphical description is used in order to organize the emulation and control. Some experimental results of a versatile testbed are given for the Peugeot $3{\infty}8$ HYbrid4.

Development of Anthropomorphic Robot Hand SKK Robot Hand I

  • Taehun Kang;Park, Hyoukryeol;Kim, Moonsang
    • Journal of Mechanical Science and Technology
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    • v.17 no.2
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    • pp.230-238
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    • 2003
  • In this paper, a three-fingered anthropomorphic robot hand, called SKK Robot Hand 1, is presented. By employing a two-DOF joint mechanism, called Double Active Universal Joint (abbreviated as DAUJ from now on) as its metacarpal joint, the hand makes it possible to mimic humanlike motions. We begin with addressing the motivation of the design and mention how the anthropomorphic feature of a human is realized in the design of SKK Hand I Also, the mechanism of the hand is explained in detail, and advantages in its modular design are discussed. The proposed hand is developed for use as a testbed for dextrous manipulation. It is expected to resolve the increasing demand for robotic applications in unstructured environments. We describe its hardware construction as well as the controller structure including the preliminary results of experiments.

An improved SRTS algorithm for DS3 rate video communication (DS3급 영상 통신을 위한 개선된 동기식 나머지 타임스탬프(SRTS) 알고리즘)

  • 이종형;김태균
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.2
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    • pp.417-426
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    • 1996
  • The end-to-end service clock recovery is a critical issue in providing constandt bit rate service through ATM network. The Synchronous Residual Time Stamp(SRTS) algorithm is used to recovery the source clock using time stamp of transmitter. In thispaper, we propose a Differential Residual Time Stamp (DRTS) transmission mechanism to effectively deliver the timing information of source clock in SRTS algorithm. The RTS transmission method simple in its hardware. From the results of field trial of DS3 rate interactive video communication system through B-ISDN testbed, it can be identified that DRTS method is superior to the RTS method.

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A Case Study of Process Monitoring System for Mold Production with Ubiquitous Technology (유비쿼터스 기술 기반의 금형제조 공정관리 시스템 사례 연구)

  • Choi, Young;Kim, Jung-Joon;Yang, Sang-Wook;Park, Jin-Pyo;Kwon, Ki-Eak
    • Korean Journal of Computational Design and Engineering
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    • v.14 no.3
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    • pp.168-175
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    • 2009
  • A recent advance in RFID technology is one of the major technological drives in reducing cost in logistics, distribution and even in the manufacturing sector. However, currently the technology is practically accepted only in the area of logistics and inventory control. The characteristic of these application areas is that the technology is used in the controllable environment. In this paper, we discuss a case study of using active and passive RFID technologies to automatically gather process information in the mold factory. Active RFID tags are attached on the main parts of molds and their positions in the floor are tracked with the routers. We also discuss on the idea of using mobile device with RFID reader to inquire information for molds on the spot in the factory floor. The inquirable information includes 3D design data and basic mold data. The paper shows implementation results with hardware configuration for the testbed.

360 Content Pilot Service Platform of Cultural Assets Based on MPEG-V Standard Realistic Media Testbed (MPEG-V 표준 실감미디어 테스트베드에 기반을 둔 문화재 360 콘텐츠 시범 서비스 플랫폼)

  • Shim, Tae-soeb;Yoo, Soo-bin;Shin, Sang-ho
    • Journal of Advanced Navigation Technology
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    • v.21 no.6
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    • pp.666-673
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    • 2017
  • In this paper, we propose a 360 content pilot service platform of cultural assets based on MPEG-V standard realistic media testbed. MPEG-V is that the standard format of sensory effect metadata(SEM) such like wind, light and flash, and communication protocol between sensory effect machines are defined, and it is possible to increase the sense of presence and immersion with 360 VR content. The proposed platform consists of software which is composed of the content player and the sensory effect reappearance server, and hardware which is the sensory effect machines. Also, the pilot service case using the proposed platform, and the features and advantages of the proposed platform are described.

Implementation of a FLEX Protocol Signal Processor for High Speed Paging System (고속 페이징 시스템을 위한 FLEX 프로토콜 신호처리기의 구현)

  • Gang, Min-Seop;Lee, Tae-Eung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.1
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    • pp.69-78
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    • 2001
  • This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

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