• Title/Summary/Keyword: hardware optimization

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Code Refactoring Techniques Based on Energy Bad Smells for Reducing Energy Consumption (Energy Bad Smells 기반 소모전력 절감을 위한 코드 리팩토링 기법)

  • Lee, Jae-Wuk;Kim, Doohwan;Hong, Jang-Eui
    • KIPS Transactions on Software and Data Engineering
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    • v.5 no.5
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    • pp.209-220
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    • 2016
  • While the services of mobile devices like smart phone, tablet, and smart watch have been increased and varied, the software embedded into such devices has been also increased in size and functional complexity. Therefore, increasing operation time of mobile devices for serviceability became an important issue due to the limitation of battery power. Recent studies focus on the software development having efficient behavioral patterns because the energy consumption of mobile devices is caused by software behaviors which control the hardware operations. However, it is often difficult to develop the embedded software with considering energy-efficiency and behavior optimization due to the short development cycle of the mobile services in many cases. Therefore, this paper proposes the refactoring techniques for reducing energy consumption, and enables to fulfill the energy requirements during software development and maintenance. We defined energy bad smells with the code patterns that can excessively consume the energy, and our refactoring techniques are to remove these bad smells. We performed some case studies to verify the usefulness of our refactoring techniques.

An MPEG-2 AAC Encoder Chip Design Operating under 70MIPS (70MIPS 이내에서 동작하는 MPEG-2 AAC 부호화 칩 설계)

  • Kang Hee-Chul;Park Ju-Sung;Jung Kab-Ju;Park Jong-In;Choi Byung-Gab;Kim Tae-Hoon;Kim Sung-Woo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.4 s.334
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    • pp.61-68
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    • 2005
  • A chip, which can fast encoder the audio data to AAC (Advanced Audio Coding) LC(Low Complexity) that is MPEG-2 audio standard, has been designed on the basis of a 32 bits DSP core and fabricated with 0.25um CMOS technology. At first, the various optimization methods for implementing the algerian are devised to reduce the memory size and calculation cycles. FFT(Fast Fourier Transform) hardware block is added to the DSP core to get the more reduction of the calculation cycles. The chips has the size of $7.20\times7.20 mm^2$ and about 830,000 equivalent gates, can carry out AAC encoding under 70MIPS(Million Instructions per Second).

A Study on the Implementation of Embedded DHCP Server Based on ARM (ARM 기반의 임베디드 DHCP서버 구축에 관한 연구)

  • Kim Hyeong-Gyun;Lee Sang-Beom
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.8
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    • pp.1490-1494
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    • 2006
  • Most network equipment is an embedded system designed to execute specific function. An embedded system is an electronic control system mixing hardware and software to execute only fixed function for the purpose of system, not confuter, performing diverse function for a wide use. Early embedded system executed only simple function, combining specific function with optimization, a micro size, and low power, but it has developed to meet complex and diverse system. The purpose of this study is to realize DHCP server based on embedded system. To achieve this, embedded Linux was ported in ez Bord-M01 mounted with Intel Strong ARM SA1110 processor, and ethernet-based network was constructed for network function. In this way, this study suggests embedded DHCP server where Window and Linux client hosts are dynamically configurated as network information by dynamically assigning network information in embedded board.

Design of Downlink Beamforming Transmitter in OFDMA/ TDD system (OFDMA/TDD 시스템의 하향링크 빔형성 송신기 설계)

  • Park Hyeong-Sook;Park Youn-Ok;Kim Cheol-Sung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.5A
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    • pp.493-500
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    • 2006
  • This paper presents the efficient structure and parameter optimization of downlink beamforming transmitter in OFDMA/TDD system. To design downlink beamforming transmitter for multiple transmit antennas, an efficient beamforming structure for multiple users and the choice of word-length of each block are critical in the aspect of its performance and hardware complexity. We propose an efficient beamforming scheme, which stores the weights of subcarriers into memory without user identification at the receiver of base station and calculates the weights for corresponding user in a subcarrier unit of IFFT input at high speed. Also, we obtain the word-length of main data path and other design parameters by fixed-point simulation analysis. The proposed architecture could reduce the memory size proportional to the maximum number of users per frame, and the processing time of an OFDM symbol at the receiver of base station without the need of additional processing time for calculating the weights at the transmitter.

A Study of Distribute Computing Performance Using a Convergence of Xeon-Phi Processor and Quantum ESPRESSO (퀀텀 에스프레소와 제온 파이 프로세서의 융합을 이용한 분산컴퓨팅 성능에 대한 연구)

  • Park, Young-Soo;Park, Koo-Rack;Kim, Dong-Hyun
    • Journal of the Korea Convergence Society
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    • v.7 no.5
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    • pp.15-21
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    • 2016
  • Recently the degree of integration of processor and developed rapidly. However, clock speed is not increased, a situation that increases the number of cores in the processor. In this paper, we analyze the performance of a typical Intel Xeon Phi of many core process used for the current operation accelerate. Utilizing the Quantum ESPRESSO, which was calculated using the FFTW library. By varying the number of ranks in MPI when running the benchmarks the performance Xeon Phi. The result shows a good performance in the handling of four job on one physical core. However, four or more to expand the number of MPI Rank is degraded. Through this convergence it was found to improve the performance of Quantum ESPRESSO. It is possible to check the hardware characteristics of the Xeon Phi.

An Energy Harvesting Aware Routing Algorithm for Hierarchical Clustering Wireless Sensor Networks

  • Tang, Chaowei;Tan, Qian;Han, Yanni;An, Wei;Li, Haibo;Tang, Hui
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.2
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    • pp.504-521
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    • 2016
  • Recently, energy harvesting technology has been integrated into wireless sensor networks to ameliorate the nodes' energy limitation problem. In theory, the wireless sensor node equipped with an energy harvesting module can work permanently until hardware failures happen. However, due to the change of power supply, the traditional hierarchical network routing protocol can not be effectively adopted in energy harvesting wireless sensor networks. In this paper, we improve the Low-Energy Adaptive Clustering Hierarchy (LEACH) protocol to make it suitable for the energy harvesting wireless sensor networks. Specifically, the cluster heads are selected according to the estimation of nodes' harvested energy and consumed energy. Preference is given to the nodes with high harvested energy while taking the energy consumption rate into account. The utilization of harvested energy is mathematically formulated as a max-min optimization problem which maximizes the minimum energy conservation of each node. We have proved that maximizing the minimum energy conservation is an NP-hard problem theoretically. Thus, a polynomial time algorithm has been proposed to derive the near-optimal performance. Extensive simulation results show that our proposed routing scheme outperforms previous works in terms of energy conservation and balanced distribution.

Comparing the performance of two hybrid deterministic/Monte Carlo transport codes in shielding calculations of a spent fuel storage cask

  • Lai, Po-Chen;Huang, Yu-Shiang;Sheu, Rong-Jiun
    • Nuclear Engineering and Technology
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    • v.51 no.8
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    • pp.2018-2025
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    • 2019
  • This study systematically compared two hybrid deterministic/Monte Carlo transport codes, ADVANTG/MCNP and MAVRIC, in solving a difficult shielding problem for a real-world spent fuel storage cask. Both hybrid codes were developed based on the consistent adjoint driven importance sampling (CADIS) methodology but with different implementations. The dose rate distributions on the cask surface were of primary interest and their predicted results were compared with each other and with a straightforward MCNP calculation as a baseline case. Forward-Weighted CADIS was applied for optimization toward uniform statistical uncertainties for all tallies on the cask surface. Both ADVANTG/MCNP and MAVRIC achieved substantial improvements in overall computational efficiencies, especially for gamma-ray transport. Compared with the continuous-energy ADVANTG/MCNP calculations, the coarse-group MAVRIC calculations underestimated the neutron dose rates on the cask's side surface by an approximate factor of two and slightly overestimated the dose rates on the cask's top and side surfaces for fuel gamma and hardware gamma sources because of the impact of multigroup approximation. The fine-group MAVRIC calculations improved to a certain extent and the addition of continuous-energy treatment to the Monte Carlo code in the latest MAVRIC sequence greatly reduced these discrepancies. For the two continuous-energy calculations of ADVANTG/MCNP and MAVRIC, a remaining difference of approximately 30% between the neutron dose rates on the cask's side surface resulted from inconsistent use of thermal scattering treatment of hydrogen in concrete.

Implementation of High Performance Overlay Multicast Packet Forwarding Engine On NetFPGA (NetFPGA를 이용한 고성능 오버레이 멀티캐스트 패킷 전송 엔진 구현)

  • Jeon, Hyuk-Jin;Lee, Hyun-Seok;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.6
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    • pp.9-17
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    • 2012
  • High-quality multimedia on the Internet has attracted attention because of its wide application area. IP multicast has been proposed as a solution to use efficient network resources in these services. However, IP multicast has not been commonly used due to a number of practical issues such as security and management. As an alternative, an overlay multicast routing which is performed in upper protocol layers on legacy networks without changing hardware has been presented. Yet, the maximum data transmission capacity of the overlay multicast is not sufficient for real time transmission of multimedia data. In this paper, we have implemented an overlay multicast engine on NetFPGA which allows us to perform packet replication and tunneling which need high-speed. In addition, we have implemented extra portions which need low-speed in software. From now on, we will progress research which increase the number of terminal spots which can be replicated by improvement and amplify throughputs by optimization.

Linearity Optimization of DC CT and a Study on the Application of HVDC System (HVDC DC CT 선형성 최적화 및 시스템 적용에 대한 연구)

  • Choi, Yong-Kil;Lee, Eun-Jae;Choi, Ho-Seok;Lee, Wook-Hwa
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.63 no.6
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    • pp.758-763
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    • 2014
  • These days, the advantages of DC power system are consistently stand out in korea that was a small power loss and high stability. Needs of DC power transmission technology is focused In the midst of a smart grid and environment friendly generation technology boom that is needed for next generation technology. Researches and businesses for HVDC(High Voltage Direct Current) system has been began. But, Needs of HVDC equipment and system commissioning technology are not on the rise until now. In particular, South Korea's HVDC technology is after the foot runner of advanced country and company. In addition, There is no experience for equipment verification and commissioning technology. And Experts of HVDC are rare. Who has been fully understood hardware and system as a whole, and identified all the equipment's characteristic. Recently, Academia and industry are recognized a needs of HVDC technology. But it does not received a recognition of technical value. In this paper, introduce issues when we apply the IEEE's verification method for HVDC system, especially DC current measurement system, DC CT(Direct Current Transformer), among the HVDC equipments. And Proposes remedial methods on the issue in order to recognize the necessity that was HVDC equipments's verification and commissioning technology research should be focused on.

Low-Power and High-Efficiency Class-D Audio Amplifier Using Composite Interpolation Filter for Digital Modulators

  • Kang, Minchul;Kim, Hyungchul;Gu, Jehyeon;Lim, Wonseob;Ham, Junghyun;Jung, Hearyun;Yang, Youngoo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.1
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    • pp.109-116
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    • 2014
  • This paper presents a high-efficiency digital class-D audio amplifier using a composite interpolation filter for portable audio devices. The proposed audio amplifier is composed of an interpolation filter, a delta-sigma modulator, and a class-D output stage. To reduce power consumption, the designed interpolation filter has an optimized composite structure that uses a direct-form symmetric and Lagrange FIR filters. Compared to the filters with homogeneous structures, the hardware cost and complexity are reduced by about half by the optimization. The coefficients of the digital delta-sigma modulator are also optimized for low power consumption. The class-D output stage has gate driver circuits to reduce shoot-through current. The implemented class-D audio amplifier exhibited a high efficiency of 87.8 % with an output power of 57 mW at a load impedance of $16{\Omega}$ and a power supply voltage of 1.8 V. An outstanding signal-to-noise ratio of 90 dB and a total harmonic distortion plus noise of 0.03 % are achieved for a single-tone input signal with a frequency of 1 kHz.