• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.9
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• pp.1652-1659
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• 2008

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.518-525
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• 2003

In this paper, we present a fast hardware architecture to implement a parallel 2-dimensional discrete wavelet transform(DWT)based on the lifting scheme DWT framework. The conventional 2-D DWT had a long initial and total latencies to get the final 2D transformed coefficients because the DWT used an entire input data set for the transformation and transformed sequentially The proposed architecture increased the parallel performance at computing the row directional transform using new data splitting method. And, we used the hardware resource sharing architecture for improving the total throughput of 2D DWT. Finally, we proposed a scheduling of hardware resource which is optimized to the proposed hardware architecture and splitting method. Due to the use of the proposed architecture, the parallel computing efficiency is increased. This architecture shows the initial and total latencies are improved by 50% and 66%.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.4 no.6
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• pp.1294-1310
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• 2010

User authentication using fingerprint information provides convenience as well as strong security. However, serious problems may occur if fingerprint information stored for user authentication is used illegally by a different person since it cannot be changed freely as a password due to a limited number of fingers. Recently, research in fuzzy fingerprint vault system has been carried out actively to safely protect fingerprint information in a fingerprint authentication system. In addition, research to solve the fingerprint alignment problem by applying a geometric hashing technique has also been carried out. In this paper, we propose the hardware architecture for a geometric hashing based fuzzy fingerprint vault system that consists of the software module and hardware module. The hardware module performs the matching for the transformed minutiae in the enrollment hash table and verification hash table. On the other hand, the software module is responsible for hardware feature extraction. We also propose the hardware architecture which parallel processing technique is applied for high speed processing. Based on the experimental results, we confirmed that execution time for the proposed hardware architecture was 0.24 second when number of real minutiae was 36 and number of chaff minutiae was 200, whereas that of the software solution was 1.13 second. For the same condition, execution time of the hardware architecture which parallel processing technique was applied was 0.01 second. Note that the proposed hardware architecture can achieve a speed-up of close to 100 times compared to a software based solution.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.8 no.5
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• pp.54-62
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• 1999

This paper describes the design and implementation of a PC(personal computer) based open architecture machine tool controller. The hardware of open architecture CNC has generally a motion control board on a PC for controlling a servo motor. But this paper describes open architecture hardware that consists of a PC, a counter board a DAC board and a DIO board only. This makes it easy to generate CNC software module in a hardware-independent way. The proposed open architecture CNC software runs on the MS-Windows NT. The paper describes a method of con-trolling servo motors using a real-time timer of MS-Windows NT and a commercial real-time operating system on the MS-Windows. NT. An open and reconfigurable software module is made up of an object and an API(application programming interface). Using the object and the API a new CNC system can be quickly configured to control dif-ferent machine tools. The proposed open architecture CNC system is applied to 4-axis lettering center.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1187-1188
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• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• Journal of Information Processing Systems
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• v.5 no.4
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• pp.187-196
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• 2009

This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.83-86
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• Journal of information and communication convergence engineering
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• v.11 no.2
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• pp.118-123
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• 2013

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.217-230
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• 2012

This paper propose interacting test programming methods between test equipment and hardware unit to verify function and performance of the hardware unit under test. Proposed test program can minimizes the risk of failures when the unit is mounted on the aircraft by testing and verifying the unit under the worst stress condition. Also, Object oriented design using UML make it easy to apply in other equipments. Test program consists of architecture package and hardware package. Architecture package is in a role for system management, log analysis, message receiving and message analysis. Messages that are used by system management define messages for testing and defined messages is sent and received to test equipment through Ethernet. Hardware package is in a role for hardware management that is needed to be tested and is related to a system. Hardware to be tested is divided into internal test and transmission test. Internal test inspects hardware itself and reports the test results to the test equipment. Transmission test inspects communication device by sending or receiving data. All kinds of test is done in the worst condition of the test unit executing in parallel. Each device is tested at least 482 times and at most 15,003 times about one hour. Test program is utilized in hardware reliability test like as environmental test or EMI test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.405-413
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• 2003

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture to efficiently implement RS (Reed-Solomon) codecs, which is one of the most widely used FEC (Forward Error Control) algorithms. The proposed DSP architecture can implement various primitive polynomials by program, and thus, hardwired codecs can be replaced. The new instructions and their hardware architecture perform GF (Galois Field) operations using the proposed GF multiplier and adder. Therefore, the proposed DSP architecture can significantly reduce the number of clock cycles compared with existing DSP chips. It can perform RS decoding rate of up to 228.1 Mbps on 130MHz DSP chips.