• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.7 no.3
• /
• pp.291-300
• /
• 2017

Quantum-dot cellular automata(QCA) is a computing model designed to be similar to cellular automata, and an alternative technology for next generation using high performance and low power consumption. QCA is undergoing various studies with recent experimental results, and it is one of the paradigms of transistors that can solve device density and interconnection problems as nano-unit materials. An XOR gate is a gate that operates so that the result is true when either one of the logic is true. The proposed XOR gate consists of five layers. The first layer consists of OR gates, the third and fifth layers consist of AND gates, and the second and fourth layers are designed as passages in the middle. The half adder consists of an XOR gate and an AND gate. The proposed half adder is designed by adding two cells to the proposed XOR gate. The proposed half adder consists of fewer cells, total area, and clock than the conventional half adder.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.7 no.10
• /
• pp.895-903
• /
• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.

• Korean Journal of Optics and Photonics
• /
• v.13 no.5
• /
• pp.421-424
• /
• 2002

By using SOA (Semiconductor Optical Amplifier) based devices, an all-optical half adder has been successfully demonstrated at 10 Gb/s. All-optical XOR and AND gates are utilized to realize SUM and CARRY. Since SUM and CARRY have been simultaneously realized to form the all-optical half adder, complex calculation and signal processing can be achieved.

• Progress in Superconductivity
• /
• v.5 no.1
• /
• pp.21-25
• /
• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• Journal of the Optical Society of Korea
• /
• v.18 no.6
• /
• pp.639-645
• /
• 2014

In this paper, the scheme of a single module for simultaneous operation of all-optical computing circuits, namely half adder and half subtractor, are realized using semiconductor optical amplifier (SOA) based logic gates. Optical XOR gate by employing a SOA based Mach-Zehnder interferometer (MZI) configuration is used to get the sum and difference outputs. A carry signal is generated using a SOA-four wave mixing (FWM) based AND gate, whereas, the borrow is generated by employing the SOA-cross gain modulation (XGM) effect. The obtained results confirm the feasibility of our configuration by proving the good level of quality factor i.e. ~5.5, 9.95 and 12.51 for sum/difference, carry and borrow, respectively at 0 dBm of input power.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.11 no.1
• /
• pp.15-22
• /
• 1974

A new ternary full adder using the current controlled negative-resistance circuit is described. The full adder is constructed from the modified-half-adder which was devised by making use of a negative resistance circuit. This full adder makes the number of its gates decrease and makes its own speed increase in comparison with the full adders which had been introduced previously. It is convenient to construct to the integrated circuit because transistor, SBD(Schottky Barrier Diode) and resistors were used as the circuit elements.

• Progress in Superconductivity
• /
• v.6 no.1
• /
• pp.7-12
• /
• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• Progress in Superconductivity
• /
• v.7 no.2
• /
• pp.109-113
• /
• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
• /
• 2003.10a
• /
• pp.117-119
• /
• 2003

We have designed fabricated, and tested an RSFQ(Rapid Single Flux Quantum) 1-bit ALU (Arithmetic Logic Unit). The 1-bit ALU was composed of a half adder and three SFQ DC switches. Three DC switches were attached to the two output ports of an ALU for the selection of each function from the available functions that were AND, OR, XOR and ADD. And we also attached two DC switches at the input ports of the half adder so that the input data were controlled using the function generators operating at low speed while we tested the circuit at high speed. The test bandwidth was from 1KHz to 5 ㎓. The chip was tested at the liquid helium temperature of 4.2 K.

• Proceedings of the Optical Society of Korea Conference
• /
• 2006.07a
• /
• pp.159-160
• /
• 2006

By using 2 signals without additional input signal, an all-optical binary half adder at 10 Gbps is demonstrated. The half adder operates in single mechanism, which is XGM. By achieving this experiment, we also explored the possibilities for the enhanced complex logic operation and higher chances for multiple logic integration.