• 한국전산유체공학회:학술대회논문집
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• 2002.05a
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• pp.158-163
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• 2002

In the present study a 3D data visualization and analysis program with stereoscopic viewing is introduced. The GUI of the program is based on Qt-library, while all the graphic rendering is performed with OpenGL library. The program allocates memory dynamically according to the data size so that the problem size is only limited by the computer's hardware memory. The stereoscopic viewing is realized by carefully-calibrated projection and color-masking of red and blue color for the left and right eye, and the only hardware needed for the stereoscopic visualization of 3D data is a cheap and easily-available red/blue glasses. Further work for addition of more functions and options to the present program will be continued.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.5
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• pp.656-662
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• 2018

Pattern matching algorithm is widely used in many application fields such as bio-informatics, intrusion detection, etc. Among many string matching algorithms, KMP (Knuth-Morris-Pratt) algorithm is commonly used because of its fast execution time when using large texts. However, the processing speed of KMP algorithm is also limited when the text size increases significantly. In this paper, we propose a high throughput parallel KMP algorithm considering CPU-GPU memory hierarchy based on OpenCL in GPGPU (General Purpose computing on Graphic Processing Unit). We focus on the optimization for the allocation of work-times and work-groups, the local memory copy of the pattern data and the failure table, and the overlapping of the data transfer with the string matching operations. The experimental results show that the execution time of the optimized parallel KMP algorithm is about 3.6 times faster than that of the non-optimized parallel KMP algorithm.

• Geophysics and Geophysical Exploration
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• v.14 no.1
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• pp.98-104
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• 2011

Numerical simulation in exploration geophysics provides important insights into subsurface wave propagation phenomena. Although elastic wave simulations take longer to compute than acoustic simulations, an elastic simulator can construct more realistic wavefields including shear components. Therefore, it is suitable for exploration of the responses of elastic bodies. To overcome the long duration of the calculations, we use a Graphic Processing Unit (GPU) to accelerate the elastic wave simulation. Because a GPU has many processors and a wide memory bandwidth, we can use it in a parallelised computing architecture. The GPU board used in this study is an NVIDIA Tesla C1060, which has 240 processors and a 102 GB/s memory bandwidth. Despite the availability of a parallel computing architecture (CUDA), developed by NVIDIA, we must optimise the usage of the different types of memory on the GPU device, and the sequence of calculations, to obtain a significant speedup of the computation. In this study, we simulate two- (2D) and threedimensional (3D) elastic wave propagation using the Finite-Difference Time-Domain (FDTD) method on GPUs. In the wave propagation simulation, we adopt the staggered-grid method, which is one of the conventional FD schemes, since this method can achieve sufficient accuracy for use in numerical modelling in geophysics. Our simulator optimises the usage of memory on the GPU device to reduce data access times, and uses faster memory as much as possible. This is a key factor in GPU computing. By using one GPU device and optimising its memory usage, we improved the computation time by more than 14 times in the 2D simulation, and over six times in the 3D simulation, compared with one CPU. Furthermore, by using three GPUs, we succeeded in accelerating the 3D simulation 10 times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.80-88
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• 2002

Visual media(image, graphic, and video) processing poses challenge from several perpectives, specifically from the point of view of real-time implementation and scalability. There have been several approaches to obtain speedups to meet the computing demands in multimedia processing ranging from media processors to special purpose implementations. A variety of parallel processing strategies are adopted in these implementations in order to achieve the required speedups. We have investigated a parallel processing system for improving the processing speed o f visual media related applications. The parallel processing system we proposed is similar to a pipelined memory stystem(MAMS). The multi-access memory system is made up of m memory modules and a memory controller to perform parallel memory access with a variety of combinations of 1${\times}$pq, pq${\times}$1, and p${\times}$q subarray, which improves both cost and complexity of control. Facial recognition, Phong shading, and automatic segmentation of moving object in image sequences are some that have been applied to the parallel processing system and resulted in faithful processing speed. This paper describes the parallel processing systems for the speedup and its utilization to three time-consuming applications.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.119-128
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• 2019

Due to the nature of the 3D graphics processor system, many mathematical calculations are required and parallel processing research using GPU (Graphics Processing Unit) is being performed for high-speed processing. In this paper, we propose a 3D graphics processor using MAMS, a parallel processor that does not use cache memory, to solve the GPU problem of increasing bandwidth caused by cache memory miss and the problem that 3D shader processing speed is not constant. The 3D graphics processor using MAMS proposed in this paper designed Vertex shader, Pixel shader, Tiling and Rasterizing structure using DirectX command analysis, the FPGA(Xilinx Virtex6@100MHz) board for MAMS was constructed and designed using Verilog. We compared the processing time of the developed FPGA (100Mhz) and nVidia GeForce GTX 660 (980Mhz), the processing time using GTX 660 was not constant and suing MAMS was constant.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.5
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• pp.298-305
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• 2003

This paper describes a 128-channel hardware simulator that is useful for verification and testing of digital circuits. It performs logic analyzer function and signal generator function at the same time. The core module, which implements one channel of the simulator, operates as a controller with independent memory and internal mode. Therefore, we can easily extend the number of channels with addition of core module. Moreover, since the simulator was implemented as a PC based system, one can construct a low-cost system and can configure convenient GUI(Graphic User Interface) environment. The simulator implemented using FPGA operates at 50Mhz and consumes 55W power as average.

• Journal of the Korean Graphic Arts Communication Society
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• v.29 no.3
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• pp.31-40
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• 2011

Using of QR(Quick Response) code is dramatically extended to various marketing area; not only substitute of bar code but also new tool of PR and marketing. This research attempts to analyze brand communication effect using QR code printed on product package especially in snack product category. Findings are 1) communication effect are different according to the type of book-trailers; 2) cinematic production and animation are the most effective type of book-trailers; 3) for memory and confirmation(sharing), a)stills and straplines, Analysis result of hypothesis I showed that characters of QR code influence on brand attitude. Among dependent variables, only reliability is significant. That means reliability of company and brand using QR code influence on brand attitude. The higher reliability of QR code, the better brand attitude of the brand. Analysis result of hypothesis II found that only reliability is significant on purchasing intention. Reliability of company and product using QR code influences on purchasing intention. The higher reliability of QR code, the higher possibility of purchasing products. Therefore, company can enhance reliability of both company and its products by using QR code. Using QR code will bring high reliability and high brand attitude and purchasing intention.

• Computational Structural Engineering
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• v.2 no.4
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• pp.69-77
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• 1989

Until recently post-processing of finite element model has been heavily relied on expensive graphic peripheral devices. With the aid of inexpensive microcomputers, very economical post-processor graphics program called MICRO-POST has been developed. Model geometry or results of analysis for the unlimited meshes can be easily presented in a number of low-cost graphic devices. The paper presents the procedure obtaining the device-independent graphics, and the structure and functions of the program. It also describes efficient I/O scheme to overcome the memory limitation, and dialogue-type input technique to control the plot operation in an interactive manner. Through the post processing examples for the general purpose finite element programs, it demonstrates the usefulness of the program.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.151-163
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• 2013

Recently the attention on digital hologram that is regarded as to be the final goal of the 3-dimensional video technology has been increased. Digital hologram is calculated by modeling the interference phenomenon between an object wave and a reference wave. The modeling for digital holograms is called by computer generated hologram (CGH) Generally, CGH requires a very large amount of calculation. So if holograms are generated in real time, high-speed method should be needed. In this paper, we analyzed CGH equation, optimized it for mapping general purpose graphic processing unit (GPGPU), and proposed a optimized CGH calculation technique for GPGPU by resource allocation and various experiments which include block size changing, memory selection, and hologram tiling. The implemented results showed that a digital hologram that has $1,024{\times}1,024$ resolution can be generated during approximately 24ms, using 1K point clouds. In the experiment, we used two GTX 580 GPGPU of nVidia Inc.