• 한국전자통신학회논문지
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• 제9권2호
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• pp.167-171
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• 2014

CVD를 이용하여 다결정 및 단결정 Cu 시편에 대한 그래핀의 합성 실험을 수행하였으며, 광학현미경 조직사진과 이미지 분석을 통하여 그래핀의 성장거동과 합성에 대한 특성평가 결과를 제시 하였다. 다결정 Cu 시편의 결정성에 따른 그래핀의 성장에 대한 분석의 결과 그래핀의 성장이 다결정 Cu 시편의 결정에 따라 일정한 방향성을 갖고 성장한다는 것을 알 수 있었으며, 다결정 Cu 시편의 이웃하는 단일 결정 내에서 성장하는 그래핀 형성에 대한 이미지 분석의 결과 단층, 복층, 그리고 3층의 그래핀에 대한 특성 분석이 가능하였다. 또한, (111) 방향을 갖는 단결정 Cu 시편을 이용하여 약 $3mm^2$ 정도의 비교적 넓은 면적을 갖는 고품질의 단일층 단결정 그래핀 합성과 이에 대한 특성평가 결과를 나타내고 있다.

• 한국전자파학회논문지
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• 제26권9호
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• pp.837-840
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• 2015

그래핀은 한 원자 두께의 탄소재료로서 전자가 매우 빠른 속도로 이 층을 통과할 수 있기 때문에, 트랜지스터를 비롯한 다양한 디바이스 응용을 위한 연구가 수행되어 왔다. 높은 전자이동도 특성으로 인해 높은 주파수 대역이나 고속 스위치 등의 시스템 응용에 적합하다. 본 연구에서는 양산에 적합한 RT-CVD(Rapid Thermal Chemical Vapor Deposition) 공정을 이용하여 실리콘 기판 상에 그래핀 층을 형성하고, 다양한 공정조건 최적화를 통해 $7,800cm^2/Vs$의 전자이동도를 추출하였다. 이는 실리콘 기판의 7배 이상 되는 값이고, GaAs 기판보다도 높은 수치이다. 밴드갭이 존재하지 않는 그래핀 기반 트랜지스터 모델링을 위해 pMOS와 nMOS의 모델을 융합하여 적용하였고, 실험을 통해 추출된 전자이동도 값을 적용하였다. 추출된 모델을 이용하여 트랜지스터의 핵심 파라미터 중의 하나인 게이트의 길이와 폭 등에 따른 전기적 특성을 고찰하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.562-562
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• 2012

Recently, graphene and graphene-based materials such as graphene oxide (GO) or reduced graphene oxide (R-GO) draws a great attention for electronic devices due to their structures of one atomic layer of carbon hexagon that have excellent mechanical, electrical, thermal, optical properties and very high specific surface area that can be high potential for chemical functionalization. R-GO is a promising candidate because it can be prepared with low-cost from solution process by chemical oxidation and exfoliation using strong acids and oxidants to produce graphene oxide (GO) and its subsequent reduction. R-GO has been used as semiconductor or conductor materials as well as sensing layer for bio-molecules or ions. In this work, reduced graphene oxide field-effect transistor (R-GO FET) has been fabricated with ITO extended gate structure that has sensing area on ITO extended gate part. R-GO FET device was encapsulated by tetratetracontane (TTC) layer using thermal evaporation. A thermal annealing process was carried out at $140^{\circ}C$ for 4 hours in the same thermal vacuum chamber to remove defects in R-GO film before deposition of TTC at $50^{\circ}C$ with thickness of 200 nm. As a result of this process, R-GO FET device has a very high stability and durability for months to serve as a transducer for sensing applications.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.80-80
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• 2010

Graphene has attracted tremendous attention for the last a few years due to it fascinating electrical, mechanical, and chemical properties. Up to now, several methods have been developed exclusively to prepare graphene, which include micromechanical cleavage, polycrystalline Ni employing chemical vapor deposition technique, solvent thermal reaction, thermal desorption of Si from SiC substrates, chemical routes via graphite intercalation compounds or graphite oxide. In particular, polycrystalline Ni foil and conventional chemical vapor deposition system have been widely used for synthesis of large-area graphene. [1-3] In this study, synthesis of mono-layer graphene on a Ni foil, the mixing ratio of hydrocarbon ($CH_4$) gas to hydrogen gas, microwave power, and growth time were systemically optimized. It is possible to synthesize a graphene at relatively lower temperature ($500^{\circ}C$) than those (${\sim}1000^{\circ}C$) of previous results. Also, we could control the number of graphene according to the growth conditions. The structural features such as surface morphology, crystallinity and number of layer were investigated by scanning electron microscopy (SEM) and atomic force microscopy (AFM), transmission electron microscopy (TEM) and resonant Raman spectroscopy with 514 nm excitation wavelength. We believe that our approach for the synthesis of mono-layer graphene may be potentially useful for the development of many electronic devices.

• 마이크로전자및패키징학회지
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• 제28권1호
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• pp.67-71
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• 2021

본 연구에서는 금속 와이어를 촉매로 화학기상증착법을 이용하여 그래핀을 합성하고 구조 및 전기적 특성 변화를 분석하였다. 구리와 니켈의 탄소에 대한 용해도 차이로 인해 구리와이어에서는 단층 그래핀이 성장하였고, 니켈와이어의 표면에는 다층 그래핀이 성장되었다. 또한. 고온의 그래핀 성장 조건에서 구리와 니켈의 재결정화를 통해 결정립의 크기가 증가한 것을 확인하였다. 표면에 그래핀이 합성된 구리와이어의 경우, 최대전류허용치는 1.91×105 A/㎠으로 합성 전 구리와이어에 비해 약 27% 향상되었다. 이와 유사하게, 다층 그래핀이 합성된 니켈와이어의 경우에도 최대전류 허용치는 순수한 니켈와이어 대비 약 36% 향상된 4.41×104 A/㎠으로 측정되었다. 이러한 그래핀/금속 복합소재의 우수한 전기적 특성은 고전류를 요구하는 소자 및 부품에서 안정적인 전기적 흐름을 공급하는데 기여할 수 있을 것이다.

• 마이크로전자및패키징학회지
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• 제29권1호
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• pp.71-75
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• 2022

Graphene oxide를 ZnCl₂:NaCl 전해질과 함께 교반한 후 순환 전압전류법에 의해 전기화학적으로 제막하여 유기태양전지용 전자수송층 제막과정을 단순화하고 이를 갖는 유기태양전지를 제작하였다. 소자의 구조는 FTO/ZnO:graphene 전자수송층/P3HT:PCBM 광활성층/PEDOT:PSS 정공수송층/Ag이다. ETL의 형태 및 화학적 특성은 주사전자현미경(scanning electron microscopy, SEM), X선 광전자 분광법(X-ray photoelectron spectroscopy, XPS), 라만 분광법으로 확인하였다. XPS 측정결과 ZnO 금속산화물 및 탄소결합이 동시에 확인되었고, 라만 분광법에서 ZnO와 graphene 피크를 확인하였다. 제작한 태양전지의 전기적 특성을 솔라시뮬레이터로 측정하였고 0.05 V/s의 속도로 2회 제막한 ETL 소자에서 1.94%의 가장 높은 광전변환효율을 나타내었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.13-13
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• 2011

Graphene based nano-electronic and nano-electromechanical devices will be introduced in this presentation. The first part of the presentation will be covered by our recent results on the fabrication and physical properties of artificially twisted bilayer graphene. Thanks to the recently developed contact transfer printing method, a single layer graphene sheet is stacked on various substrates/nano-structures in a controlled manner for fabricating e.g. a suspended graphene device, and single-bilayer hybrid junction. The Raman and electrical transport results of the artificially twisted bilayer indicates the decoupling of the two graphene sheets. The graphene based electromechanical devices will be presented in the second part of the presentation. Carbon nanotube based nanorelay and A new concept of non-volatile memory based on the carbon nanotube field effect transistor together with microelectromechanical switch will be briefly introduced at first. Recent progress on the graphene based nano structures of our group will be presented. The array of graphene resonators was fabricated and their mechanical resonance properties are discussed. A novel device structures using carbon nanotube field effect transistor combined with suspended graphene gate will be introduced in the end of this presentation.

• 한국재료학회지
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• 제30권3호
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• pp.142-148
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• 2020

Graphene has attracted the interest of many researchers due to various its advantages such as high mobility, high transparency, and strong mechanical strength. However, large-area graphene is grown at high temperatures of about 1,000 ℃ and must be transferred to various substrates for various applications. As a result, transferred graphene shows many defects such as wrinkles/ripples and cracks that happen during the transfer process. In this study, we address transfer-free, large-scale, and high-quality monolayer graphene. Monolayer graphene was grown at low temperatures on Ti (10nm)-buffered Si (001) and PET substrates via plasma-assisted thermal chemical vapor deposition (PATCVD). The graphene area is small at low mTorr range of operating pressure, while 4 × 4 ㎠ scale graphene is grown at high working pressures from 1.5 to 1.8 Torr. Four-inch wafer scale graphene growth is achieved at growth conditions of 1.8 Torr working pressure and 150 ℃ growth temperature. The monolayer graphene that is grown directly on the Ti-buffer layer reveals a transparency of 97.4 % at a wavelength of 550 nm, a carrier mobility of about 7,000 ㎠/V×s, and a sheet resistance of 98 W/□. Transfer-free, large-scale, high-quality monolayer graphene can be applied to flexible and stretchable electronic devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.209.2-209.2
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• 2015

Two dimensional layered materials, such as transition metal dichalcogenides (TMDs) family have been attracted significant attention due to novel physical and chemical properties. Among them, molybdenum disulfide ($MoS_2$) has novel physical phenomena such as absence of dangling bonds, lack of inversion symmetry, valley degrees of freedom. Previous studies have shown that the interface of metal/$MoS_2$ contacts significantly affects device performance due to presence of a scalable Schottky barrier height at their interface, resulting voltage drops and restricting carrier injection. In this study, we report a new device structure by using few-layer graphene as the bottom interconnections, in order to offer Schottky barrier free contact to bi-layer $MoS_2$. The fabrication of process start with mechanically exfoliates bulk graphite that served as the source/drain electrodes. The semiconducting $MoS_2$ flake was deposited onto a $SiO_2$ (280 nm-thick)/Si substrate in which graphene electrodes were pre-deposited. To evaluate the barrier height of contact, we employed thermionic-emission theory to describe our experimental findings. We demonstrate that, the Schottky barrier height dramatically decreases from 300 to 0 meV as function of gate voltages, and further becomes negative values. Our findings suggested that, few-layer graphene could be able to realize ohmic contact and to provide new opportunities in ohmic formations.

• 한국전기전자재료학회논문지
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• 제31권2호
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• pp.112-116
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• 2018

Electric double layer capacitors (EDLCs) are promising candidates for energy storage devices in electronic applications. An EDLC yields high power density but has low specific capacitance. Carbon material is used in EDLCs owing to its large specific surface area, large pore volume, and good mechanical stability. Consequently, the use of carbon materials for EDLC electrodes has attracted considerable research interest. In this paper, in order to evaluate the electrochemical performance, graphene is used as an EDLC electrode with flake sizes of 3, 12, and 60 nm. The surface characteristic and electrochemical properties of graphene were investigated using SEM, BET, and cyclic voltammetry. The specific capacitance of the graphene based EDLC was measured in a 1 M $TEABF_4/ACN$ electrolyte at the scan rates of 2, 10, and 50 mV/s. The 3 nm graphene electrode had the highest specific capacitance (68.9 F/g) compared to other samples. This result was attributed to graphene's large surface area and meso-pore volume. Therefore, large surface area and meso-pore volume effectively enhances the specific capacitance of EDLCs.