• Journal of Power Electronics
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• v.9 no.6
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• pp.854-865
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• 2009

Super-lift dc-dc converters are a series of advanced step-up dc-dc topologies that provide high voltage transfer gains by super-lift techniques. This paper presents a developed graphical modelling method for super-lift converters and gives a thorough analysis with a consideration of the effects caused by parasitic parameters and diodes' forward voltage drop. The general guidelines for constructing and deriving graphical models are provided for system analysis. By applying it to examples, the proposed method shows the advantages of high convenience and feasibility. Both the circuit simulation and experimental results are given to support the theoretical analysis.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10d
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• pp.649-651
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• 2002

제어 흐름 그래프는 프로그램의 문장들간의 제어 흐름 정보를 표현하는 방법이다. 제어 흐름 정보는 프로그램 분석과 테스팅 분야에서 필요로 하는 정보이다. 제어 흐름 정보가 정확할수록 정확한 분석 결과와 테스팅 결과를 구할 수 있다. 실제 자바 프로그램에서 예외 구문의 사용빈도가 많으므로 예외 제어 흐름을 제어 흐름 정보에 포함해야 한다. 본 논문에서는 특정 분석에 무관하게 예외 제어 흐름을 포함하는 제어 흐름 그래프를 생성하는 일반적인 방법을 제안한다. 그리고 예외 제어 흐름을 포함하는 제어 흐름 그래프를 생성할때, 정상 흐름과 예외 흐름을 분리해서 하는 방법을 제안한다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.298-300
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• 2002

급격한 기술의 발전 및 신기술의 등장에 따라 국가적 차원에서 고속, 대량의 데이터를 처리하는 네트워크를 구축할 필요성이 발생하였다. 이에 고속 통신망을 구축, 운영 중에 있으나, 현재의 network은 망의 안정성, 생존성 확보를 위하여 다수의 장거리 전용회선을 사용하고 있다. 본 논문에서는 현재의 network 구조에 피터슨 그래프를 이용하여 약간의 수정을 가하여 기존 운영중인 망에서 생존성을 보장하고 경제성을 향상시키는 효율적 망 활용 방법을 제시한다.

• ETRI Journal
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• v.31 no.2
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• pp.240-242
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• 2009

A computationally efficient implementation of the progressive edge-growth algorithm is presented. This implementation uses an array of red-black (RB) trees to manage the layered structure of check nodes and adopts a new strategy to expand the Tanner graph. The complexity analysis and the simulation results show that the proposed approach reduces the computational effort effectively. In constructing a low-density parity check code with a length of $10^4$, the RB-tree-array-based implementation takes no more 10% of the time required by the original method.

• Journal of Educational Research in Mathematics
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• v.27 no.3
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• pp.411-430
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• 2017

This study examined the understanding of 24 pre-service teachers about the three contexts for constructing the exponential graphs. The three contexts consisted of the infinite points context (2009 revision curriculum textbook method), the infinite straight lines context (French textbook method), and the continuous compounding context (2015 revision curriculum textbook method). As the result of the examination, most of the pre-service teachers selected the infinite points context as easier context for introducing the exponential graph. They noted that it was the appropriate method because they thought their students would easily understand, but they showed the most errors in the graph presentation of this method. These errors are interpreted as a lack of content knowledge. In addition, a number of pre-service teachers noted that the infinite straight lines context and continuous compounding context were not appropriate because these contexts can aggravate students' difficulty in understanding. What they pointed out was interpreted in terms of knowledge of content and students, but at the same time those things revealed a lack of content knowledge for understanding the continuous compounding context. In fact, considering the curriculum they have experienced, they were not familiar with this context, continuous compounding. These results suggest that pre-service teacher education should be improved. Finally, some of the pre-service teachers mentioned that using technology can help the students' difficulties because they considered the design of visual model.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1353-1362
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• 1999

그래프 드로잉이란 추상적인 그래프를 시각적으로 구성하여 2차원 평면상에 그려주는 작업으로 대칭성은 그래프 드로잉시 고려해야 하는 미적 기준들 중에서 그래프의 구조 및 특성을 표현해주는 가장 중요한 기준이다. 그러나 일반 그래프에서 대칭성을 찾아 그려 주는 문제는 NP-hard로 증명이 되어 있기 때문에 현재까지는 트리, 외부평면 그래프, 직병렬 유향 그래프나 평면 그래프 등으로 대상을 한정시켜 연구가 진행되어 왔다. 본 논문에서는 병렬 컴퓨터나 컴퓨터 네트워크 구조를 가시화 시키기 위하여 많이 사용되는 그래프인 상호연결망(interconnection network)의 대칭성을 분석하고 분석된 대칭성을 최대로 보여주는 대칭 드로잉 알고리즘을 제안하였다. 그리고 이를 기반으로 하여 상호연결망의 기존 드로잉 방법들과 본 논문에서 제안한 대칭 드로잉 등 다양한 드로잉을 지원하는 WWW 기반의 상호연결망 드로잉 시스템을 구현하였다.Abstract Graph drawing is constructing a visually-informative drawing of an abstract graph. Symmetry is one of the most important aesthetic criteria that clearly reveals the structures and the properties of graphs. However, the problem of finding geometric symmetry in general graphs is NP-hard. So the previous work has focused on the subclasses of general graphs such as trees, outerplanar graphs, series-parallel digraphs and planar graphs.In this paper, we analyze the geometric symmetry on the various interconnection networks which have many applications in the design of computer networks, parallel computer architectures and other fields of computer science. Based on these analysis, we develope algorithms for constructing the drawings of interconnection networks which show the maximal symmetries.We also design and implement Interconnection Network Drawing System (INDS) on WWW which supports the various drawings including the conventional drawings and our suggested symmetric drawings.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.1-12
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• 1999

A new algorithm of constructing binary decision diagram(BDD) for design verification of switch-level circuits is proposed in this paper. In the switch-level circuit, functions are characterized by serial and parallel connections of switches and the final logic values may have high-impedance and unstable states in addition to the logic values of 0 and 1. We extend the BDD to represent functions of switch-level circuits as acyclic graphs so called switch-level binary decision diagram (SLBDD). The function representation of the graph is in the worst case, exponential to the number of inputs. Thus, the ordering of decision variables plays a major role in graph sizes. Under the existence of pass-transistors and domino-logic of precharging circuitry, we also propose an input ordering algorithm for the efficiency in graph sizes. We conducted several experiments on various benchmark circuits and the results show that our algorithm is efficient enough to apply to functional simulation, power estimation, and fault-simulation of switch-level design.

• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.61-69
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• 2012

BIRS is an intermediate representation for verifying Java program. Java program in the form of bytecode could be translated into BIRS code. Verification conditions are generated from the BIRS code to verify the program. We propose a method generating verification conditions for BIRS code. Generating verification conditions is composed of constructing control flow graph for BIRS code, depth first searching for the control flow graph to generate basic paths, and calculating weakest preconditions of the basic paths.

• Journal of Korea Multimedia Society
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• v.20 no.3
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• pp.533-542
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• 2017

Novels include various character names, depending on the genre and the spatio-temporal background of the novels and the nationality of characters. Besides, characters and their names in a novel are created by the author's pen and imagination. As a result, any proper noun dictionary cannot include all kinds of character names. In addition, the novels translated into Korean have character names consisting of two or more nouns (such as "Harry Potter"). In this paper, we propose a method to extract noun phrases for character names and to cluster the noun phrases into coreferents for the same character name. In the extraction of noun phrases, we utilize KKMA morpheme analyzer and CPFoAN character identification tool. In clustering the noun phrases into coreferents, we construct a directed graph with the character names extracted by CPFoAN and the extracted noun phrases, and then we create name sets for characters by traversing connected subgraphs in the directed graph. With four novels translated into Korean, we conduct a survey to evaluate the proposed method. The results show that the proposed method will be useful for speaker identification as well as for constructing the social network of characters.

• Journal of Korea Multimedia Society
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• v.3 no.1
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• pp.77-90
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• 2000

Real-Time verification is a procedure that verifies the correctness of specification related to requirement in time as well as in logic. One serious problem encountered in the verification task is that the state space grows exponentially owing to the unboundedness of time, which is termed the state space explosion problem. In this paper, we propose a real-time verification technique checking the correctness of specification by showing that a system model described in timed automata is equivalent to the characteristic of system property specified in timed modal-mu calculus. For this, we propose a local model checking method based on the value of the formula in initial state with constructing product graph concerned to only the nodes needed for verification process. Since this method does not search for every state of system model, the state space is reduced drastically so that the proposed method can be applied effectively to real-time system verification.