• 한국정보과학회논문지:시스템및이론
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• 제26권10호
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• 제어로봇시스템학회논문지
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• 제5권4호
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• pp.462-470
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• 1999

In this paper, we proposed a cross-couple controller for compensating nonlinear friction of the X-Y table of CNC machines. Due to the nonlinearity of the frictions, large contour errors, referred to as quadrant glitches, occur when each axis of the X-Y table makes a zero velocity crossing. To reduce the quadrant glitches the friction compensators and nonlinear friction observers for estimating Coulomb frictions are employed in the proposed method. A hyperbolic tangent function is used in reducing the magnitude of quadrant glitches and the CEM (Contour Error Model) is utilized for the estimation of the velocities. The performance of the proposed compensators is evaluated for several trajectories by computer simulations.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2000년도 가을 학술발표논문집 Vol.27 No.2 (3)
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• pp.41-43
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• 2000

멀티미디어 시스템에서는 미디어 데이터의 연속성을 보장하는 것이 중요한 문제이다. 90년대에 제안된 구역분할 디스크에서 연속성을 보장하면서 멀티미디어를 효과적으로 저장, 전송하기 위하여 새로운 스케줄링 방식과 데이터 블록의 배치가 제안되었다. 이 방식은 구역을 순환하면서 데이터 블록을 배치시키고 SCAN 알고리즘으로 데이터를 읽어 들이는 방식이다. 이 경우 SCAN 알고리즘으로 데이터를 읽어 들이므로 이중 버퍼링(double buffering) 방법을 사용하게 된다. 이중 버퍼링의 데이터를 읽어 들이는 주기와 서비스 주기의 불일치성으로 인하여 새로운 스트림의 요청이 있을 때 기존의 서비스 스트림에 주기시간의 증가로 인한 데이터의 지연문제(jitter)가 발생한다. 본 논문에서는 구역분할 디스크를 이용하는 비디오 서버에서 새로운 요구의 도착으로 인하여 발생하는 데이터 지연 문제(jitter)를 해결하기 위하여 선행 버퍼링이란 기법을 제시한다.

• 한국통신학회논문지
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• 제22권11호
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• pp.2521-2530
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• 1997

In this paepr, we present a video-on-demand (VOD) system design model that address and integrates a number of inter-related issues. Then with analysis and performance evaluation, we investigate various aspects of disk and buffer managements in the given model. Based on the analysis results, we suggest that a distributed buffering scheme with intermediate buffers may te useful to transform bursty disk accesses into a continuous stream for for glitch-free performance of VOD systems. Also, through simulation, we illustrate that massive multimedia information storage design techniques such as prefetching, clustered striping, and real-time disk scheduling integrated with the distributed buffering mechanism may enhance end-to-end real-time performance of VOD systems under wide-area networks.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.518-521
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• 1998

This paper describes a 3.3V-65MHz 12BIT CMOS current-mode DAC designed with a 8 MSB current matirx stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch ahs been employed. The simulation results of the designed DAC show a coversion rate of 65MHz, a powr dissipation of 71.7mW, a DNL of .+-.0.2LSB and an INL of .+-.0.8LSB with a single powr supply of 3.3V for a CMOS 0.6.mu.m n-well technology.

• 산업기술연구
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• 제24권A호
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• pp.83-90
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• 2004

Generally, electronic appliances are used on the basis of normal power source supply. The power source inevitably includes the abnormal condition, such as, sudden voltage sagging, power interrupt, and induced noises. As the electronic appliances which include micro-controller-based circuits are being increased recently, the controller circuit sometimes malfunctions by the abnormal condition of the power source. This situation causes serious problems such as hitch of electric appliance, fire and medical instrument glitch, which produces serious situations. In this paper, development of power interrupt tester which is highly suitable for an endurance test device under abnormal power source to microprocessor-based circuits is proposed 89C2051 microcontroller is performed to make power interrupt signal, and software controls peripheral hardwares and built-in functions. Experimental results of this study will offer a good application to electronic appliance maker as a test device of hardware and software debugging use.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.689-692
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• 1999

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.181-187
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• 2003

This paper presents an 125MHz, 128-phase phase-locked loop using interpolation technique for digital timing recovery. To reduce the power consumption and chip area, phase interpolation was performed over only selected windows, instead of overall period. Four clocks were used for phase interpolation to avoid the output jitter increase due to the interpolation clock (clock used for phase interpolation) switching. Also, the output clock was fed back to finite-state machine (FSM) where the multiplexer selection signals are generated to eliminate the possible output glitches. The PLL implemented in a $0.25\mu\textrm{m}$ CMOS process and dissipates 80mW at 2.5V supply and occupies $0.84\textrm{mm}^2.

• 제어로봇시스템학회논문지
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• 제19권11호
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• pp.991-997
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• 2013

In this paper, we propose a CFWC (CCD and fuzzy PID based width control) scheme to obtain the desired delivery width margin of a vertical rolling mill in hot strip process. A WMS(width measurement system) is composed of two line scan cameras, an edge detection algorithm, a glitch filter, and so on. A dynamic model of the mill is derived from a gauge meter equation in order to design the fuzzy PID controller. The controller is a self-learning structure to select the PID gains from the error and error rate of the width margin. The effectiveness of the proposed CFWC is verified from simulation results under a width disturbance of the entry in the mill. Using a field test, we show that the performance of the width control is improved by the proposed control scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.873-879
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• 2016

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is $490{\mu}A$ from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.