• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.2
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• pp.324-334
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• 2017

The simulators for a plant unit master control (UMC) developed by domestic or overseas researchers have been developed for operator-training purposes. UMC simulators normally constructed at the end of the plant construction, despite the UMC logics, should be simulated to pre-check many signal interfaces within the power generation systems. Because of the differences in construction schedule, it is difficult for logic designers or commissioning engineers to simulate the UMC logic during the design or commissioning stage. In this background, this paper proposes a simulation method that can be used easily by plant logic designers or operators in the MATLAB Simulink programming environment. The core of the UMC is realized with a unique simulation algorithm based on mathematical analysis and functional blocks combination. In addition, an integer-based configuration was proposed to realize the plant target value control for the equipment in the logic. With these simulation methods, functions, e.g., load distribution, high-low limitations, frequency compensation, etc. were simulated. The results showed that the plant UMC logic can be simulated in Simulink without a plant simulator. The various functions proposed in this paper can provide useful information about Simulink-based simulation design for plant logic designers or commissioning engineers during the power plant construction period.

• Journal of KIISE:Software and Applications
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• v.35 no.3
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• pp.149-161
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• 2008

As Programmable Logic Controllers(PLCs) are frequently used to implement real-time safety critical software, testing of PLC software is getting more important. We propose a structural testing technique on Function Block Diagram(FBD) which is one of the PLC programming languages. In order to test FBD networks, we define templates for function blocks including timer function blocks and propose an algorithm based on the templates to transform a unit FBD into a flowgraph. We generate test cases by applying existing testing techniques to the generated flowgraph. While the existing FBD testing technique do not consider infernal structure of FBD to generate test cases and can be applied only to FBD from which the specific intermediate model can be generated, this approach has advantages of systematic test case generation considering infernal structure of FBD and applicability to any FBD without regard to its intermediate format. Especially, the proposed method enables FBD networks including timer function blocks to be tested thoroughly. To demonstrate the effectiveness of the proposed method, we use trip logic of bistable processor of digital nuclear power plant protection systems which is being developed in Korea.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.12
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• pp.1250-1260
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• 2014

In this paper, a novel resource scheduling, which is used for hub network based long distance airborne tactical communication, is proposed. Recently, some countries of the world has concentrated on developing data rate and networking performance of CDL, striving to keep pace with modern warfare, which is changed into NCW. And our government has also developed the next generation high capacity CDL. In hub network, a typical communication structure of CDL, hybrid FDMA/TDMA can be considered to exchange high rate data among multiple UAVs simultaneously, within limited bandwidth. However, due to different RTT and traffic size of UAV, idle time resource and unnecessary packet transmission delay can occur. And these losses can reduce entire efficiency of hub network in long distance communication. Therefore, in this paper, we propose RTT and data traffic size based UAV scheduling, which selects time/frequency resource of UAVs by using iterative sorting algorithm. The simulation results verified that the proposed scheme improves data rate and packet delay performance in low complexity.

• Journal of Korea Water Resources Association
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• v.47 no.10
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• pp.921-934
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• 2014

The purpose of the study is to derive a long term reservoir operation method that is easy to understand and apply to practical use for dam operators. The zone based operation rule is a simple method to make operation decisions by criteria corresponding to storage zones. The reservoir storage levels dividing a reservoir, however, must be determined by some methods. We developed a reservoir operation model based on the zone based operation rule and the shuffled complex evolution algorithm (SCE-UA) was used to determine storage levels for zone division. The model was applied to Angat Dam in the Philippines that has trouble in water supply due to imbalance between supply and demand. We derived a zone based operation rule for Angat Dam and applied it to the reservoir simulation of Angat Dam using the historical inflow. The simulation results showed water supply deficit and power generation were improved by 34.5% and 21.2%, respectively, when compared with the historical records. The current study results may be used to derive a long term reservoir operation rule.

• Journal of Korean Society of Transportation
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• v.10 no.1
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• pp.55-62
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• 1992

교통수요는 교통정책 및 교통시설 계획의 수립 및 평가에 중요한 영향을 미치게 되므로 교통수요의 예측은 교통연구에서 중요한 부문을 차지하고 있다. 도로밑에 설치된 전자차량감지기(Electronic Vehicle Detector)로부터 자동 수집된 링크 교통량 자료(Traffic Counts)를 주요 입력자료로 이용하여 계획지역의 기종점 통행표(Origin Destination Trip Matrix)를 작성할 수 있는 기법 들이 최근 수년동안 많이 발달하게 되었다. 이러한 새로운 기법들은 가구조사(Home Inteview), 노변면접조사(Road-Side Interview)등을 토하여 조사된 자료를 기초로하는 전통적은 4단계 교통수요추정방법(Conventional 4-Stage Estimation Method)-통행발생(Generation), 통행분포(Distribution), 수단선택(Modal Split), 교통배분(Assignment)-과 비교하여 첫째로 정확도가 높은 링크 교통량 자료를 별도의 조사를 거치지 않고서도 수집이 가능하기 때문에 조사비용이 거의 들지 않아도 되어 경제적이고, 둘째로 전통적인 수요예측방법들에서 요구되어지는 복잡한 모형수립 및 계수조정(Parameter Calibration)이 필요하지 않아 간편하고 셋째로 오래전에 작성된 기종점 통행표를 단순히 링크 교통량 자료만을 이용하여 쉽게 보완할 수 있어 지속적인 자료의 축적(Data Age-ing)이 가능하며 더 나아 가서 소위 연속적인 교통 계획 및 교통시설관리(Continuous Transport Planning and Management)를 가능케 하는 등의 여러 장점 때문에 많은 주목을 받아 오고 최근 몇 년이 꾸준히 실무에 유용하게 적용이 되고 있는 실정이다. 본 연구는 링크 교통량자료를 이용하여 기종점 통행표를 작성하기 위하여 개발된 기존의 여러 기법들 가운데 특히 용량제약조건(Capacity-Restrained Condition)하에서 기존의 방법들을 상호 검토한 후 Wardrop의 교통망 평형원칙(Wardrop's First Network Equilibrium Principle)을 만족하는 새로운 추정기법을 제의하고 이의 시험결과를 논의하는 것을 주요내용으로 한다. 링크 교통량 자료를 이용하여 기종점 통행표를 작성하는 기법들의 근본 목표는 조사된 링크 교통량(Ob-served Traffic Counts)에 가장 근접한 교통망 통행 배정 링크 교통량(Assigned Link Volumes)을 재현(Re-producing)할 수 있는 기종점 통행표들 중에서 최적의 기종점 통행표를 발견하는 것이다. 따라서 교통망에서 통행자의 여행 경로 배정을 가장 잘 반영할 수 있는 현실적인(Realistic) 교통망 통행 배정 모형(Net-work Traffic Assignment Model)의 선택은 중요한 요소가 되며 특히 교통망에 교통체증(Traffic Conges-tion)이 심할 경우 교통망 통행자 평형조건(Network Traffic Equilibrium Condition)을 고려하기 위한 특별한 처리가 요구되어진다. 본 연구는 Whllumsen(Hall, Van Vliet and Willumsen, 1980)에 의하여 개발된 ME2(Maximum Entropy Matrix Estimation)기법에서 반복식 추정방법(Sequential Estimation Method)을 사용할 경우 Wardrop의 평형조건을 만족하는 기종점 통행표를 구할 수 없다는 단점을 극복하기 위한 방안으로서 엔트로피 극대화문제와 교통망 평형 조건(Entropy Maximisation and Network Equilibrium Condition)의 두 문제를 동시에 해결할 수 있는 새로운 수식모형과 이를 풀기 위한 알고리즘(Simultaneous Solution Algorithm)을 제의하였다. 제의된 수식모형과 알고리즘을 예제 교통망(Example Network)을 이용한 시험하고 그 결과를 ME2 의 반복식 추정 방법으로부터 구한 기종점 통행표와 비교 검토하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.34-44
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• 2006

A system-on-a-chip (SoC) design uses pre-verified IP hardware blocks in order to reduce design time. We need interface circuits to connect IPs with different protocols. In SoC design we should design interface circuits frequently and these tasks are somewhat time-consuming and error-prone. So it is necessary to generate the interface circuits automatically. Several studies have been made on generating interface circuits only from the communication protocols of IPs. With existing approaches, it is not easy to generate interface circuits connecting two IPs only from communication protocols: connection between IP with address and W without address, connection between IP with only one port to transfer address/data and IP with different ports for address and data connection between IP that transfer address and data together and IP that transfer only one address with a number of data in a burst. No consideration of various characteristics of IPs and no changed algorithm are responsible for it. In order to solve this problem, the proposed approach categorizes communication protocols of IPs, and takes characteristics matching of IPs into account during the interface synthesis. In experiments, we show that we could correctly generate and verify interface circuits for IPs with different characteristics.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.5
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• pp.46-54
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• 2011

In this paper, we propose a low-complexity loop filtering method depending on transform-block regions. Block adaptive loop filter (BALF) was developed to improve about 10% in compression performance for the next generation video coding. The BALF employs the Wiener filter that makes reconstructed frames close to the original ones and transmits filter-related information. However, the BALF requires high computational complexity, while it can achieve high compression performance because the block adaptive loop filter is applied to all the pixels in blocks. The proposed method is a new loop filter that classifies pixels in a block into inner and boundary regions based on the characteristics of the integer transform and derives optimum filters for each region. Then, it applies the selected filters for the inner and/or boundary regions. The decoder complexity can be adjusted by selecting region-dependent filter to be used in the decoder side. We found that the proposed algorithm can reduce 35.5% of computational complexity with 2.56% of compression loss, in case that only boundary filter is used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.80-88
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• 2007

High adaptability and scalability are two critical issues in implementing a very complex system in a single chip. To obtain high adaptability and scalability, novel system design methodology known as communication-based system design has gained large attention from SoC designers. NoC (Network-on-Chip) is such an on-chip communication-based design approach for the next generation SoC design. To provide high adaptability and scalability, NoCs employ network interfaces and routers as their main communication structures and transmit and receive packetized data over such structures. However, data packetization, and routing overhead in terms of run time and area may cost too much compared with conventional SoC communication structure. Therefore, in this research, we propose a novel methodology which automatically generates a hybrid communication structure. In this work, we map traditional pin-to-pin wiring structure for frequent and timing critical communication, and map flexible and scalable structure for infrequent, or highly variable communication patterns. Even though, we simplify the communication structure significantly through our algorithm the connectivity or the scalability of the communication modules are almost maintained as the original NoC design. Using this method, we could improve the timing performance by 49.19%, and the area taken by the communication structure has been reduced by 24.03%.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.8
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• pp.107-114
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• 2017

In this paper, a novel power factor compensation system based on voltage-controlled method is proposed for 3-phase 4-wire power system. The proposed voltage-controlled power factor compensation system generates a reactive power required for compensation by applying a variable output voltage by a slidac to a capacitor. In conventional power factor compensation system using the capacitor bank method, the power factor compensation error occurs depending on the load condition due to the limited capacity of the capacitors. However, the proposed system compensates the power factor up to 100% without error. In this paper, we have developed a voltage-controlled power factor compensation system and a control algorithm for 3-phase 4-wire power system, and verify its performance through simulation and experiments. If the proposed power factor compensation system is applied to an industrial field, a power factor compensation performance can be maximized. As a result, it is possible to reduce of electricity prices, reduce of line loss, increase of load capacity, ensure the transmission margin capacity, and reduce the amount of power generation.

• Journal of Broadcast Engineering
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• v.20 no.5
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• pp.706-717
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• 2015

The computer generated hologram (CGH) method is the technology which can generate a hologram by using only a personal computer (PC) commonly used. However, the CGH method requires a huge amount of calculational time for the 3D object with a super multi-light source or a high-definition hologram. Hence, some solutions are obviously necessary for reducing the computational complexity of a CGH algorithm or increasing the computing performance of hardware. In this paper, we propose a method which can generate a digital hologram of the 3D object with a super multi-light source using parallel distributed computing. The traditional methods has the limitation of improving CGH performance by using a single PC. However, the proposed method where a server PC efficiently uses the computing power of client PCs can quickly calculate the CGH method for 3D object with super multi-light source. In the experimental result, we verified that the proposed method can generate the digital hologram with 1,5361,536 resolution size of 3D object with 157,771 light source in 121 ms. In addition, in the proposed method, we verify that the proposed method can reduce generation time of a digital hologram in proportion to the number of client PCs.