• Title/Summary/Keyword: gating

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Do N37 and P37 Potentials Have Different Generators in Somatosensory Evoked Potential? - Analysis Using Gating Mechanism - (체성감각 유발전위에서 N37과 P37은 다른 발생기를 가지고 있는가? - gating 현상을 이용한 분석 -)

  • Park, Young Seok;Cha, Jae Kwan;Kim, Sang Ho;Kim, Jae Woo
    • Annals of Clinical Neurophysiology
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    • v.1 no.2
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    • pp.106-111
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    • 1999
  • Backgroud : The generators of N37 and P37 of posterior tibial nerve somatosensory evoked potential(PTSEP) have not been exactly known. Recently, some reports suggested that P37 and N37 might have different generator. We conducted a study to know the generators of P37 and N37 of PTSEP using gating mechanism. Methods : We evaluated subcortical and cortical somatosensoy evoked potentials(SEPs) in response to posterior tibial nerve stimulation in 3 experimental conditions of foot movement and compared them with PTSEPs in full relaxation of foot. The experimental conditions were: (a) active flexion-extention of stimulated foot, (b) isometric contraction of the stimulated foot, (c) passive flexion-extention of the stimulate foot. We analyzed the latencies and amplitudes of following potentials; P30, N37, P37, and N50. Results : The amplitude of P30 potential did not change during at any paradigms. The amplitudes of P37 and N50 were significantly attenuated in all condition. However, the amplitude of N37 showed no significant change during at any paradigms. Conclusions : These results suggest that the generators of P37 and N37 of PTSEP be different in cortex.

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Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique

  • Yang, Yil-Suk;Roh, Tae-Moon;Yeo, Soon-Il;Kwon, Woo-H.;Kim, Jong-Dae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.1
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    • pp.1-7
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    • 2009
  • This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

A 2.5-V, 1-Mb Ferroelectric Memory Design Based on PMOS-Gating Cell Structure (PMOS 게이팅 셀 기반 2.5-V, 1-Mb 강유전체 메모리 설계)

  • Kim, Jung-Hyun;Chung, Yeonbae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.10 s.340
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    • pp.1-8
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    • 2005
  • In this paper, a FRAM design style based on PMOS-gating cell structure is described. The memory cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) $V_{DD}$ precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore, Because this configuration doesn`t need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for a 2.5-V, 1-Mb FRAM prototype design in a $0.25-{\mu}m$, triple-well technology shows a chip size of $3.22\;mm^{2}$, an access time of 48 ns and an active current of 11 mA. The cell efficiency is 62.52 $\%$. It has gained approximately $20\;\%$ improvement in the cell array efficiency over the conventional plate-driven FRAM scheme.

Asn-Linked Glycosylation Contributes to Surface Expression and Voltage-Dependent Gating of Cav1.2 Ca2+ Channel

  • Park, Hyun-Jee;Min, Se-Hong;Won, Yu-Jin;Lee, Jung-Ha
    • Journal of Microbiology and Biotechnology
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    • v.25 no.8
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    • pp.1371-1379
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    • 2015
  • The Cav1.2 Ca2+ channel is essential for cardiac and smooth muscle contractility and many physiological functions. We mutated single, double, and quadruple sites of the four potential Asn (N)-glycosylation sites in the rabbit Cav1.2 into Gln (Q) to explore the effects of Nglycosylation. When a single mutant (N124Q, N299Q, N1359Q, or N1410Q) or Cav1.2/WT was expressed in Xenopus oocytes, the biophysical properties of single mutants were not significantly different from Cav1.2/WT. In comparison, the double mutant N124,299Q showed a positive shift in voltage-dependent gating. Furthermore, the quadruple mutant (QM; N124,299,1359,1410Q) showed a positive shift in voltage-dependent gating as well as a reduction of current. We tagged EGFP to the QM, double mutants, and Cav1.2/WT to chase the mechanisms underlying the reduced currents of QM. The surface fluorescence intensity of QM was weaker than that of Cav1.2/WT, suggesting that the reduced current of QM arises from its lower surface expression than Cav1.2/WT. Tunicamycin treatment of oocytes expressing Cav1.2/WT mimicked the effects of the quadruple mutations. These findings suggest that Nglycosylation contributes to the surface expression and voltage-dependent gating of Cav1.2.

Electrophysiological Characteristics of Six Mutations in hClC-1 of Korean Patients with Myotonia Congenita

  • Ha, Kotdaji;Kim, Sung-Young;Hong, Chansik;Myeong, Jongyun;Shin, Jin-Hong;Kim, Dae-Seong;Jeon, Ju-Hong;So, Insuk
    • Molecules and Cells
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    • v.37 no.3
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    • pp.202-212
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    • 2014
  • ClC-1 is a member of a large family of voltage-gated chloride channels, abundantly expressed in human skeletal muscle. Mutations in ClC-1 are associated with myotonia congenita (MC) and result in loss of regulation of membrane excitability in skeletal muscle. We studied the electrophysiological characteristics of six mutants found among Korean MC patients, using patch clamp methods in HEK293 cells. Here, we found that the autosomal dominant mutants S189C and P480S displayed reduced chloride conductances compared to WT. Autosomal recessive mutant M128I did not show a typical rapid deactivation of Cl- currents. While sporadic mutant G523D displayed sustained activation of $Cl^-$ currents in the whole cell traces, the other sporadic mutants, M373L and M609K, demonstrated rapid deactivations. $V_{1/2}$ of these mutants was shifted to more depolarizing potentials. In order to identify potential effects on gating processes, slow and fast gating was analyzed for each mutant. We show that slow gating of the mutants tends to be shifted toward more positive potentials in comparison to WT. Collectively, these six mutants found among Korean patients demonstrated modifications of channel gating behaviors and reduced chloride conductances that likely contribute to the physiologic changes of MC.

Gated Clock-based Low-Power Technique based on RTL Synthesis (RTL 수준에서의 합성을 이용한 Gated Clock 기반의 Low-Power 기법)

  • Seo, Young-Ho;Park, Sung-Ho;Choi, Hyun-Joon;Kim, Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.3
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    • pp.555-562
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    • 2008
  • In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

Effect of Gate Number on the Characteristics of Interface between Cast and Forged Insert (게이트 수에 따른 단조형 인서트와 주물재 사이의 경계부 특성 분석)

  • Lee, S.M.;Yi, H.K.;Lee, G.Y.;Mun, S.M.;Moon, Y.H.
    • Journal of the Korean Society for Heat Treatment
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    • v.22 no.2
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    • pp.95-100
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    • 2009
  • In this study, the casting process using forged insert was investigated to characterize the manufacturing process by which good mechanical properties can be obtained when compared with existing casting products. Process analysis for the casting design was performed by using FVM (Finite Volume Method) software. In pouring process, three kinds of candidate gating systems are considered and analyzed respectively. The molten metal behavior in gating system is so important that it affects the solidification behavior of the cast. The results show that as the number of gates is increased, hardness of cast was increased and gaps of cast with forged insert were decreased.

Low-Power Systolic Array Viterbi Decoder Implementation With A Clock-gating Method (Clock-gating 방법을 사용한 저전력 시스톨릭 어레이 비터비 복호기 구현)

  • Ryu Je-Hyuk;Cho Jun-Dong
    • The KIPS Transactions:PartA
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    • v.12A no.1 s.91
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    • pp.1-6
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    • 2005
  • This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

High-Performance Optical Gating in Junction Device based on Vanadium Dioxide Thin Film Grown by Sol-Gel Method

  • Lee, Yong-Wook;Kim, Eung-Soo;Shin, Bo-Sung;Lee, Sang-Mae
    • Journal of Electrical Engineering and Technology
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    • v.7 no.5
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    • pp.784-788
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    • 2012
  • In this paper, a high-performance optical gating in a junction device based on a vanadium dioxide dioxide ($VO_2$) thin film grown by a sol-gel method was experimentally demonstrated by directly illuminating the $VO_2$ film of the device with an infrared light at ~1554.6 nm. The threshold voltage of the fabricated device could be tuned by ~76.8 % at an illumination power of ~39.8 mW resulting in a tuning efficiency of ~1.930 %/mW, which was ~4.9 times as large as that obtained in the previous device fabricated using the $VO_2$ thin film deposited by a pulsed laser deposition method. The rising and falling times of the optical gating operation were measured as ~50 ms and ~200 ms, respectively, which were ~20 times as rapid as those obtained in the previous device.

Intracellular cAMP-modulated Gate in Hyperpolarization Activated Cation Channels

  • Park, Kyung-Joon;Shin, Ki-Soon
    • Animal cells and systems
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    • v.11 no.2
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    • pp.169-173
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    • 2007
  • Hyperpolarization-activated nonselective cation channels (HCNs) play a pivotal role in producing rhythmic electrical activity in the heart and the nerve cells. In our previous experiments, voltage-dependent $Cd^{2+}$ access to one of the substituted cysteines in S6, T464C, supports the existence of an intracellular voltage-dependent activation gate. Direct binding of intracellular cAMP to HCN channels also modulates gating. Here we attempted to locate the cAMP-modulated structure that can modify the gating of HCN channels. SpHCN channels, a sea urchin homologue of the HCN family, became inactivated rapidly and intracellular cAMP removed this inactivation, resulting in about eight-fold increase of steady-state current level. T464C was probed with $Cd^{2+}$ applied to the intracellular side of the channel. We found that access of $Cd^{2+}$ to T464C was strongly gated by cAMP as well as voltage. Release of bound $Cd^{2+}$ by DMPS was also gated in a cAMP-dependent manner. Our results suggest the existence of an intracellular cAMP-modulated gate in the lower S6 region of spHCN channels.