• 대한전자공학회논문지SD
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• 제37권3호
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• pp.6-13
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• 2000

실리콘 기판에 질소를 이온주입한 다음에 게이트 산화막을 2nm, 3nm, 4nm 두께로 성장시켰다. 질소이온주입 에너지는 25keV로 고정하였고 이온주입량은 5.0×10/sup l3//cm/sup 2/과1.0×10/sup 14//cm/sup 2/으로 나누어서 진행하였다. 질소이온주입량과 산화막의 성장률은 밀접한 관계가 있으며 질소이온주입량이 많아지면 산화막의 성장시간이 늘어난다. 같은 두께를 기르는데 필요한 산화시간을 질소이온주입을 하지 않은 경우와 비교하면 질소이온 주입량이 5.0×10/sup 13//cm/sup 2/ 일 때는 약 20%, 1.0×10/sup 14//cm/sup 2/일 때는 약 50% 정도 산화시간이 증가한다. 질소이온 주입량이 증가함에 따라 Q/sub BD/값은 감소하는데 이의 개선을 위해 질소이온주입후에 N/sub 2/분위기에서 850℃ 60분간 열처리를 한 다음 산화막을 성장시키면 Q/sub BD/값이 증가하여 개선됨을 보인다. 이것은 질소이온주입으로 인한 손상이 게이트 산화막의 신뢰성에 나쁜 영향을 미치지만 이온주입직후에 적절한 열처리 공정을 거치면 이러한 손상으로 인한 영향을 없앨 수 있다는 것을 의미한다.

• E2M - 전기 전자와 첨단 소재
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• 제7권1호
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• pp.57-63
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• 1994

Aluminum oxide($Al_2{O_3}$) offers some unique advantages over the conventional silicon dioxide( $SiO_{2}$) gate insulator: greater resistance to ionic motion, better radiation hardness, possibility of obtaining low threshold voltage MOS FETs, and possibility of use as the gate insulator in nonvolatile memory devices. We have undertaken a study of the dielectric breakdown of $Al_2{O_3}$ on Si deposited by GAIVBE technique. In our experiments, we have varied the $Al_2{O_3}$ thickness from 300.angs. to 1400.angs. The resistivity of $Al_2{O_3}$ films varies from 108 ohm-cm for films less than 100.angs. to 10$_{13}$ ohm-cm for flims on the order of 1000.angs. The flat band shift is positive, indicating negative charging of oxide. The magnitude of the flat band shift is less for negative bias than for positive bias. The relative dielectric constant was 8.5-10.5 and the electric breakdown fields were 6-7 MV/cm(+bias) and 11-12 MV/cm (-bias).

• 대한전자공학회논문지
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• 제23권1호
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• pp.65-73
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• 1986

Experiment have been conducted about thin oxide characteristics according to O2/N2 ratio needed for EEPROM cell fabrication. As a result, we think that there is no problem even if we grow oxide layer with large O2/N2 ratio and short exidation time and when the water is implated by As before oxidation, the oxide breakdown field is about IMV/cm lower than that is not implanted. Especially, the thin oxide characteristic seems to be affected largely by wafer cleaning and oxidation in air. On the basis of these, tunnel type EEPROM cell is fabricated by 3um CMOS process and its characteristic is studied. Tunnel oxide thickness(100\ulcorner is chosen to allow Fowler-Nordheim tunneling to charge the floating gate at the desired programming voltage and tunnel area(2x2um\ulcorneris chosen to increase capacitive coupling ratio. For program operation, high voltage (20-22V) is applied to the control gate, while both drain and source are gdrounded. The drain voltage for erase is 16V. It is shown that charge retention characteristics is not limited by leakage in the oxide and program/erase endurance is over 10E4 cycles of program erase operation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 춘계학술대회
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• pp.688-690
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• 2017

항복전압의 감소는 채널길이 감소에 의하여 발생하는 심각한 단채널 효과이다. 트랜지스터 동작 중에 발생하는 단채널 효과는 트랜지스터의 동작범위를 감소시키는 문제를 발생시킨다. 본 논문에서는 10 nm 이하 채널길이를 갖는 이중게이트 MOSFET에서 채널크기의 변화를 파라미터로 하여 채널도핑에 따른 항복전압의 변화를 고찰하였다. 이를 위하여 해석학적 전위분포에 의한 열방사 전류와 터널링 전류를 구하고 두 성분의 합으로 구성된 드레인 전류가 $10{\mu}A$가 될 때, 드레인 전압을 항복전압으로 정의하였다. 결과적으로 채널 도핑농도가 증가할수록 항복전압은 크게 증가하였다. 채널길이가 감소하면서 항복전압이 크게 감소하였으며 이를 해결하기 위하여 실리콘 두께 및 산화막 두께를 매우 작게 유지하여야만 한다는 것을 알 수 있었다. 특히 터널링 전류의 구성비가 증가할수록 항복전압이 증가하는 것을 관찰하였다.

• 전자공학회논문지D
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• 제34D권8호
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• pp.26-34
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• 1997

To develop ultrathin gate oxide for ULSI MOSFETs, for the first time, we fabricated MOS capacitors with 65.angs. thick initial oxide grown by high pressure oxidation (HIPOX) at 700.deg. C in 5 atmosphere $O_{2}$ ambient and then followed by rapid thermal nitridation (RTN) in N$_{2}$O ambient. The dielectric breakdown fields of the initial HIPOX oxide are 13.0 MV/cm and 13.8MV/cm for negative and positive gate bias, respectively and are dependent on nitridation temeprature and time.The lifetimes of the HIPOX oxides extractd by TDDB method are 1.1*10$^{8}$ sec and 3.4 * 10$^{9}$ sec for negative and positive stress current, respectively. The lifetime of the HIPOX oxide dfor negative stress current increases with nitridation time in N$_{2}$O ambient at 1100.deg.C, reaching maximum value stress curretn increases with nitridation time in N$_{2}$O ambient at 1100.deg. C reacing maximum value of 1.2*10$^{9}$ sec for 30 sec of nitridation time, and then subsequently decreases at the longer nitridation time. The lifetimes of the nitrided-HIPOX oxides are longer than 10 years when nitridations are carried out longer than about 50 sec and 12 sec at 1000.deg. C, and 1100.deg. C, respectively.

• Journal of Electrical Engineering and Technology
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• 제8권5호
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• pp.1157-1162
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• 2013

We proposed AlGaN/GaN high-electron-mobility transistors (HEMTs) using thermal oxidation for NiOx passivation. Auger electron spectroscopy, secondary ion mass spectroscopy, and pulsed I-V were used to study oxidation features. The oxidation process diffused Ni and O into the AlGaN barrier and formed NiOx on the surface. The breakdown voltage of the proposed device was 1520 V while that of the conventional device was 300 V. The gate leakage current of the proposed device was 3.5 ${\mu}A/mm$ and that of the conventional device was 1116.7 ${\mu}A/mm$. The conventional device exhibited similar current in the gate-and-drain-pulsed I-V and its drain-pulsed counterpart. The gate-and-drain-pulsed current of the proposed device was about 56 % of the drain-pulsed current. This indicated that the oxidation process may form deep states having a low emission current, which then suppresses the leakage current. Our results suggest that the proposed process is suitable for achieving high breakdown voltages in the GaN-based devices.

• 한국전기전자재료학회논문지
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• 제32권3호
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 추계학술대회 논문집
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• pp.90-93
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• 1992

In this paper, MOS characteristics of gate dielectrics prepared by furnace oxidation of Si in an $N_2O$ ambient have been studied. Compared with the oxides grown in $O_2$, $N_2O$ oxides show significantly improved breakdown field and low flat band voltage. Also, $N_2O$ oxide is more controllable for ultrathin film growth than $O_2$ oxide. This improvement is caused by nitrogen incorporation into the $N_2O$ oxide. Therefore, the nitrogen-rich-layer at the Si/$SiO_2$ interface formed during $N_2O$ oxidation not only strengthen $N_2O$ oxide structure at the interface and improves the gate dielectric quality, it also acts as a oxidant diffusion barrier that reduces the oxidation rate significantly.

• 대한전자공학회논문지
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• 제26권5호
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• pp.52-59
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• 1989

얇은 산화막의 신뢰성을 정전류 스트레스 방법으로 조사하였다. 실험에 사용된 소자는 산화막 두께가 20~25nm인 다결정실리콘 MOS 커패시터 이었다. VLSI 신뢰성 평가에 필수적인 자동측정 및 통계적 데이타분석을 HP9000 컴퓨터를 이용하여 수행하였다.측정한 TDDB 결과로부터 산화막의 결합밀도, 절연파괴 전하량(Qbd), 수명등을 측정한 결과 스트레스를 가하는 극성에 따라서 다른 특성이 나타났다. 결함밀도는 (-) 게이트 주입의 경우에 62개$cm^2$ 이었다. 절연파괴 전하량은 (+) 게이트 주입의 경우 30C/$cm^2$이었고, (-)게이트 주입의 경우가 1.43$cm^2$/A 이었고, (+)게이트 주입의 경우가 1.25$cm^2$/A이었다.