• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.284-288
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• 2013

Power MOSFETs(Metal Oxide Semiconductor Field Effect Transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. We have experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical MOSFET. The device is fabricated as $8.25{\mu}m$ cell pitch and $4.25{\mu}m$ gate width. The performances of device with various p base doping concentration are compared at Vth from 1.77 V to 4.13 V. Also the effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for various applications can be further optimized at power device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.6
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• pp.462-467
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• 2013

In this paper, we analyzed the effects of doctoring process on the patterns of Ag ink in gravure off-set printing. The parameters of doctoring process were the angle and the pressure, which was represented by the depth of blade movement to the gravure roll, of doctor blade to the surface of gravure roll, and the angle of patterns engraved on the gravure roll to the doctor blade moving direction. The proper parameters were extracted for the fine patterns and they were 15 mm for the pressure, $60^{\circ}$ for the blade angle. And the angle of patterns with respect to the blade movement should be less than $40^{\circ}$ for the best results. The gravure off-set printing with the above parameters was carried out to print gate electrodes and scan bus lines of OTFT-backplane for e-paper. The line width of $50{\mu}m$ was successfully obtained. The thickness of electrodes was $2.5{\mu}m$ and the surface roughness was $0.65{\mu}m$ and the sheet resistance was $15.8{\Omega}/{\Box}$.

• Transactions of the Korean Society of Mechanical Engineers
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• v.3 no.4
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• pp.151-157
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• 1979

An experomental study on drg reduction in the rough tubes is presunted using the drrective drag reducing proymer solutions. The friction factors of the rough tubes follow the maximum drag reduction asymptote for the lower Reynolds numbers in the turbulent flow. However, as the Reynols number is increased the rougher tube results deviate from the maximum drag rduction asymptote sooner than the less rough tube results. There appears a systematic deviation from the maximum drag reduction asymptote depending on the relative roughness just as friction factors for the Newtonian hluid inthe rough tubes exhibit in the turbulent region. The minor loss results inthe various fittings such as elbows, tees, and gate valves are presunted The fittings show higher values of the loss coefficient in the drag reducing polymer solutions than in the Newtonian fluid, which is quite contrary to the drag reduction phenomenon in the straight tubes. The eqivalent length of the fittings for the drag reducing polymer solutions is many times longer than that for Newtonian fluids due to the increase of the loss coefficient and the decrease of the friction factor. It is speculated that the solid-like behavior of the polymer solutions in the abruptly changing folw passage plays a significant role in increasing the loss coefficient.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.3
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• pp.7-12
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• 2013

In Die casting process, the problem of die degradation is often issued. In oder to increase of die life the material degradation of die steel was investigated using test core pins. Three test core pins were positioned in front of the gate entry and observed washout and soldering resistance during Mg die casting process. The test parameters are set as different commercial die materials, coatings condition and hardness of die surface. Usign 220t magnesium die casting machine was employed to cast AZ91 magnesium alloys. After 150 shots, macroscopic observation of die surface was carried out. Additional 50 cycles later, test pins were chemically cleaned with 5% HCl aqueous solution to find out the existence of washout and soldering layers. Microstructural characterization of die surface and the die roughness measurement were performed together. Computational simulation using AnyCasting program was also beneficial to correlate the extent of die damage with the position of test pin inside die cavity. As results, the optimal combination of die steel with productive coating as well as its hardness was drawn out. it will be helpful to decide the material and condition considering increasing of tool life.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.79-79
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• 2013

Quantum-structures with nanoparticles have been attractive for various electronic and photonic devices [1,2]. In recent, nonvolatile memories such as nano-floating gate memory (NFGM) and resistance random access memory (ReRAM) have been studied using silicides, metals, and metal oxides nanoparticles [3,4]. In this study, we fabricated nonvolatile memories with silicides (WSi2, Ti2Si, V2Si) and metal-oxide (Cu2O, Fe2O3, ZnO, SnO2, In2O3 and etc.) nanoparticles embedded in polyimide matrix, and photovoltaic device also with SiC nanoparticles. The capacitance-voltageand current-voltage data showed a threshold voltage shift as a function of write/erase voltage, which implies the carrier charging and discharging into the metal-oxide nanoparticles. We have investigated also the electrical properties of ReRAM consisted with the nanoparticles embedded in ZnO, SiO2, polyimide layer on the monolayered graphene. We will discuss what the current bistability of the nanoparticle ReRAM with monolayered graphene, which occurred as a result of fully functional operation of the nonvolatile memory device. A photovoltaic device structure with nanoparticles was fabricated and its optical properties were also studied by photoluminescence and UV-Vis absorption measurements. We will discuss a feasibility of nanoparticles to application of nonvolatile memories and photovoltaic devices.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.1-5
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.116-125
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• 2006

We have presented a nanoelectromechanical (NEM) model based on atomistic simulations. Our models were applied to a NEM device as called a nanotube random access memory (NRAM) operated by an atomistic capacitive model including a tunneling current model. We have performed both static and dynamic analyses of a NRAM device. The turn-on voltage obtained from molecular dynamics simulations was less than the half of the turn-on voltage obtained from the static simulation. Since the suspended carbon nanotube (CNT) oscillated with the amplitude for the oscillation center under an externally applied force, the quantity of the CNT-gold interaction in the static analysis was different from that in the dynamic analysis. When the gate bias was applied, the oscillation centers obtained from the static analysis were different from those obtained from the dynamics analysis. Therefore, for the range of the potential difference that the CNT-gold interaction effects in the static analysis were negligible, the vibrations of the CNT in the dynamics analysis significantly affected the CNT-gold interaction energy and the turn-on voltage. The turn-on voltage and the tunneling resistance obtained from our tunneling current model were in good agreement with previous experimental and theoretical works.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.155-165
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• 2001

By suggesting a mixed-mode transient simulation method utilizing a 2-dimensional device simulator, we have analyzed CDM ESD Phenomena in CMOS chips, which utilize NMOS transistors as ESD protection devices. By analyzing the simulation results, the mechanisms leading to device failures in CDM discharge and the differences in discharge characteristics with different polarities of stored charges have been explained in detail. The effects of changes in interconnection resistance values on the gate-oxide failure at input buffers, which is the most serious problem in CDM discharge, have been examined. Also improvements in discharge characteristics with addition of the NMOS transistor for input-buffer protection have been examined.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.813-815
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• 2008

We prepared highly transparent and conductive Oxide/Metal/Oxide(OMO) multilayer by sputtering and developed wet etching process of OMO with a clear edge shape for the first time. The transmittance and sheet-resistance of the OMO are about 89% and $3.3\;{\Omega}/sq.$, respectively. We adopted OMO as a gate electrode of transparent TFT (TTFT) array and integrated OLED on top of the TTFT to result in high aperture ratio of bottom emission AM-OLED.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.186-189
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• 2006

The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and room temperature process. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing process. The OTFT array with dielectric layer and organic active semiconductor layer formed at room temperature or at a temperature lower than $40^{\circ}C$. The microcontact printing process using SAM and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even submicron size, and reduced the fabrication process by 10 steps compared with photolithography. Since the process was done in room temperature, there was no pattern shrinkage, transformation, and bending problem appeared. Also, it was possible to improve electric field mobility, to decrease contact resistance, to increase close packing of molecules by SAM, and to reduce threshold voltage by using a big dielectric.