• Journal of IKEEE
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• v.22 no.2
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• pp.344-349
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• 2018

Low temperature variation of electrical characteristics for AlGaN/GaN/HEMT was studied. To investigate the effect of temperatures, transistor was cool down to $-178^{\circ}C$ and electrical characteristics were measured. The drain current density of an AlGaN/GaN HEMT with a gate length of $2{\mu}m$ was increased from 264 mA/mm to 388 mA/mm and the maximum transconductance was increased from 105 mS/mm to 134 mS/mm by decreasing the temperature to $-108^{\circ}C$. Also, the threshold voltage was shifted -0.39 V with the temperature. The reason for the variations was seemed to the reduced channel resistance corresponding to the temperature. However, most of the variation of the electrical characteristics takes places above $-108^{\circ}C$.

• Journal of Advanced Navigation Technology
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• v.18 no.4
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• pp.364-370
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• 2014

In this paper, high reliable trench formation technique and a novel fabrication techniques for trench gate MOSFET is proposed which is a key to expend application of power MOSFET in the future. Trench structure has been employed device to improve Ron characteristics by shrinkage cell pitch size in DMOSFET and to isolate power device part from another CMOS device part in some power integrated circuit. A new process method for fabricating very high density trench MOSFETs using mask layers with oxide spacers and self-align technique is realized. This technique reduces the process steps, trench width and source and p=body region with a resulting increase in cell density and current driving capability and decrease in on resistance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.2
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• pp.169-179
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• 1999

In this paper, a GaAs MESFET single-ended resistive mixer with high linearity and isolation is designed. The bias voltage of this mixer is applied only gate of GaAs MESFET to use the channel resistance. The LO is applied the gate and the RF is applied the drain through 7-pole hairpin bandpass filter to obtain the proper isolation thru LO-RF. The IF is extracted from the source with short circuit and lowpass filter. Using extracted equivalent circuits for LO and RF, conversion loss is calculated and compared with result of harmonic balance analysis. Measured conversion loss of this S-band down converter mixer is 8.2~10.5dB by considering the measured 3.0~3.4dB RF 7-pole hairpin bandpass filter loss and IP3in is 26.5dBm at Vg=-0.85~-1.0V in distortion performance.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2003.05a
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• pp.41-41
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• 2003

텅스텐(W)은 높은 thermal stability 와 process compatibility 및 우수한 corrosion r resistance 둥으로 integrated circuit (IC)의 gate 및 interconnection 둥으로의 활용이 대두되고 있으며, 차세대 thin film transistor liquid crystal display (TFT-LCD)의 gate 및 interconnection m materials 둥으로 사용되고 았다. 그러나, 이러한 장점을 가지고 있는 팅스텐 박막이 실제 공정상에 적용되가 위해서는 건식 식각이 주로 사용되는데, 이는 wet chemical 을 이용한 습식 식각을 사용할 경우 낮은 etch rate, line width 의 감소 및 postetch residue 잔류 동의 문제가 발생하기 때문이다. 또한 W interconnection etching 을 하기 위해서는 높은 텅스텐 박막의 etch rate 과 하부 layer ( (amorphous silicon 또는 poly-SD와의 높은 etch selectivity 가 필수적 이 라 할 수 있다. 그러 나, 지금까지 연구되어온 결과에 따르면 텅스탠과 하부 layer 와의 etch selectivity 는 2 이하로 매우 낮게 관찰되고 았으며, 텅스텐의 etch rate 또한 150nm/min 이하로 낮은 값을 나타내고 있다. 따라서 본 연구에서는 halogen-based inductively coupled plasma 를 이용하여 텅스텐 박막 식각시 여러 가지 첨가 가스에 따른 높은 텅스탠 박막의 etch rate 과 하부 layer 와의 높은 etch s selectivity 를 얻고자 하였으며, 그에 따른 식각 메커니즘에 대하여 알아보고자 하였다. $CF_4/Cl_2$ gas chemistry 에 첨 가 가스로 $N_2$와 Ar을 첨 가할 경 우 텅 스텐 박막과 하부 layer 간의 etch selectivity 증가는 관찰되지 않았으며, 반면에 첨가 가스로 $O_2$를 사용할 경우, $O_2$의 첨가량이 증가함에 따라 etch s selectivity 는 계속적으로 증가렴을 관찰할 수 있었다. 이는 $O_2$ 첨가에 따라 형성되는 WOF4 에 의한 텅스텐의 etch rates 의 감소에 비하여, $Si0_2$ 등의 형성에 의한 poly-Si etch rates 이 더욱 크게 감소하였기 때문으로 사료된다. W 과 poly-Si 의 식각 특성을 이해하기 위하여 X -ray photoelectron spectroscopy (XPS)를 사용하였으며, 식각 전후의 etch depth 를 측정하기 위하여 stylus p pmfilometeT 를 이용하였다.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.49-54
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• 2003

We have investigated the effects of hydrogen annealing on the physical and electrical properties of $SrBi_{2}Ta_{2}O_9(SBT)$ thin films in the Pt/SBT/Si (MFS) structure and Pt/SBT/Pt (MFM) one, respectively. The microstructure and electrical characteristics of the SBT films were deteriorated after hydrogen annealing due to the damage of the SBT films during the annealing process. To investigate the reason of the degradation of the SBT films in this work, in particular, the effect of the Pt top electrodes, SBT thin films deposited on Si, Pt, respectively, were annealed with the same process conditions. From the XRD, XPS, P-V, and C-V data, it was seen that the SBT itself was degraded after $H_2$ annealing even without the Pt top electrodes. In addition, the degradation of the SBT films after $H_2$ annealing was accelerated by the catalytic reaction of the Pt top electrodes which is so-called hydrogen degradation. To prevent this phenomenon, we proposed the alternative top electrode material, i.e. Ir, and the electrical properties of the SBT thin films were examined in the $Ir/IrO_2/SBT/IrO_2$ structures before and after the H$_2$ annealing and recovery heat-treatment processes. From the results of the P-V measurement, it could be concluded that Ir is one of the promising candidate as the electrode material for degradation resistance in the MFM structure using SBT thin films.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.2
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• pp.810-818
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• 2021

A leakage current of ESS is classified mainly by the occurrence from a PCS(Power Conditioning System) section and an unbalanced grid current. The reason for the leakage current from the PCS section is a voltage change by IGBT (Insulated Gate Bipolar Transistor) switching and stray capacitance between the IGBT and heatsink. The leakage current caused by the grid unbalanced current flows to the ESS through the neutral line of grid-connected transformer for the ESS with a three limb iron type of Yg-wire connection. This paper proposes a mechanism for the occurrence of leakage current caused by stray capacitance, which is calculated using the heatsink formula, from the aspect of the PCS section and grid unbalance current. Based on the proposed mechanisms, this study presents the modeling of the leakage current occurrence using PSCAD/EMTDC S/W and evaluates the characteristics of leakage currents from the PCS section and grid unbalanced current. From the simulation result, the leakage current has a large influence on the battery side by confirming that the leakage current from the PCS is increased from 7[mA] to 34[mA], and the leakage current from an unbalanced load to battery housing is increased from 3.96[mA] to 10.76[mA] according to the resistance of the housings and the magnitude of the ground resistance.

• Polymer(Korea)
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• v.36 no.6
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• pp.677-684
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• 2012

Injection molding process is a popular polymer processing involving plasticizing and enforcing the material flow into the mold. A polymer material shrinks according to temperature variations during the shaping process, and subsequently molding shrinkage developed. Developed deflections or warpages after molding process in part are caused by residual stress relaxation contained in the part. Adding inorganic materials or fibers such as glass and carbon to control shrinkage and enhance warpage resistance are common. In this study, warpages according to part design have been investigated through experiment. Warpages for molding conditions and mold designs such as gate locations were measured. Warpages along flow direction and perpendicular to the flow direction were also measured. Warpages near gate and far from gate were compared. Glass fiber reinforced crystalline polymers, PP and PA66 have been used in this experiment. Glass fiber reinforced crystalline polymers showed large warpage compared with glass reinforced amorphous polymers. Warpages in crystalline polymers were less influenced by molding conditions compared with amorphous polymers, however warpages of crystalline polymers significantly depend on part design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.95-102
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• 2001

Nano-scale gate length MOSFET devices require extremely shallow source/drain eftension region with junction depth of 20∼30nm. In this work, 20nm $n^{+}$-p junctions that are realized by using this $As_{2}^{+}$ low energy ($\leq$10keV) implantation show the lower sheet resistance of the $1.0k\Omega$/$\square$ after rapid thermal annealing process. The $As_{2}^{+}$ implantation and RTA process make it possible to fabricate the nano-scale NMOSFET of gate length of 70nm. $As_{2}^{+}$ 5 keV NMOSFET shows a small threshold voltage roll-off of 60mV and a DIBL effect of 87.2mV at 100nm gate length devices. The electrical characteristics of the fabricated devices with the heavily doped and abrupt $n^{+}$-p junctions ($N_{D}$〉$10^{20}$$cm^{-3}$, $X_{j}$$\leq$20nm) suggest the feasibility of the nano-scale NMOSFET device fabrication using the $As_{2}^{+}$ low energy ion implantation.

• Polymer(Korea)
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• v.36 no.5
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• pp.555-563
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• 2012

Warpage of injection molded product is caused by non-uniform shrinkage during shaping operation and relaxation of residual stress. Robust part design and glass fiber reinforced reins have been adopted to prevent warpage of part. Warpages for part designs have been investigated in this study according to the injection molding conditions. Part design contains flat specimen and two different rib designs in the flat part. Resins used in this study were glass fiber reinforced amorphous plastics, PC and ABS. Different rib designs showed significant differences of warpages in the parts. Various warpages have been observed in the three regions of the part, near gate region, opposite region to the gate, and flow direction region. Results of computer simulation revealed that the warpages were strongly related to glass fiber orientation. Flat specimen showed the smallest warpage and the specimen with ribs to the flow direction showed a high resistance to warpage. Warpage highly depended upon part design rather than molding condition. It was concluded that the rib design and selection of gate location in injection molding would be the most important factors for the control of warpage since those are directly related to the fiber orientation during molding.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.3
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.