• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.163-163
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• 2015

The effect of nematic liquid crystal(5CB-4-Cyano-4'-pentylbiphenyl) on the amorphous indium gallium zinc oxide thin film transistors(a-IGZO TFTs) was investigated. Through dropping the 5CB on the a-IGZO TFT's channel layer which is deposited by RF-magnetron sputtering, properties of a-IGZO TFTs was dramatically improved. When drain bias was induced, 5CB molecules were oriented by Freedericksz transition generating positive charges to one side of dipoles. From increment of the capacitance by orientation of liquid crystals, the drain current was increased, and we analyzed these phenomena mathematically by using MOSFET model. Transfer characteristic showed improvement such as decreasing of subthreshold slope(SS) value 0.4 to 0.2 and 0.45 to 0.25 at linear region and saturation region, respectively. Furthermore, in positive bias system(PBS), prevention effect for electron trapping by 5CB liquid crystal dipoles was observed, which showing decrease of threshold voltage shift [(${\delta}V$]_TH) when induced +20V for 1~1000sec at the gate electrode.

• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.63.1-63
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• 2003

Catalytic chemical vapor deposition (Cat-CVD) has been developed to deposit alumina(Al$_2$O$_3$) thin films on silicon (Si) crystal using N$_2$ bubbled tir-methyl aluminium [Al(CH$_3$)$_3$, TMA] and molecular oxygen (O$_2$) as source species and tungsten wires as a catalyzer. The catalyzer dissociated TMA at approximately 600$^{\circ}C$ The maximum deposition rate was 18 nm/min at a catalyzer temperature of 1000 and substrate temperature of 800$^{\circ}C$. Metal oxide semiconductor (MOS) diodes were fabricated using gates composed of 32.5-nm-thick alumina film deposited as a substrate temperature of 400oC. The capacitance measurements resulted in a relatively dielectric constant of 7, 4, fixed charge density of 1.74*10e12/$\textrm{cm}^2$, small hysteresis voltage of 0.12V, and very few interface trapping charge. The leakage current was 5.01*10e-7 A/$\textrm{cm}^2$ at a gate bias of 1V.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.200-200
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• 2003

Polycrystalline Si(polysilicon) TFTs have opened a way for the next generation of display devices, due to their higher mobility of charge carriers relative to a-Si TFTs. The polysilicon W applications extend from the current Liquid Crystal Displays to the next generation Organic Light Emitting Diodes (OLED) displays. In particular, the OLED devices require a stricter control of properties of gate oxide layer, polysilicon layer, and their interface. The polysilicon layer is generally obtained by annealing thin film a-Si layer using techniques such as solid phase crystallization and excimer laser annealing. Typically laser-crystallized Si films have grain sizes of less than 1 micron, and their electrical/dielectric properties are strongly affected by the presence of grain boundaries. Impedance spectroscopy allows the frequency-dependent measurement of impedance and can be applied to inteface-controlled materials, resolving the respective contributions of grain boundaries, interfaces, and/or surface. Impedance spectroscopy was applied to laser-annealed Si thin films, using the electrodes which are designed specially for thin films. In order to understand the effect of grain size on physical properties, the amorphous Si was exposed to different laser energy densities, thereby varying the grain size of the resulting films. The microstructural characterization was carried out to accompany the electrical/dielectric properties obtained using the impedance spectroscopy, The correlation will be made between Si grain size and the corresponding electrical/dielectric properties. The ramifications will be discussed in conjunction with active-matrix thin film transistors for Active Matrix OLED.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.284-288
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• 2013

Power MOSFETs(Metal Oxide Semiconductor Field Effect Transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. We have experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical MOSFET. The device is fabricated as $8.25{\mu}m$ cell pitch and $4.25{\mu}m$ gate width. The performances of device with various p base doping concentration are compared at Vth from 1.77 V to 4.13 V. Also the effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for various applications can be further optimized at power device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.497-497
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• 2013

Semiconducting amorphous InGaZnO (a-IGZO) has attracted significant research attention as improved deposition techniques have made it possible to make high-quality a-IGZO thin films. IGZO thin films have several advantages over thin film transistors (TFTs) based on other semiconducting channel layers.The electron mobility in IGZO devices is relatively high, exceeding amorphous Si (a-Si) by a factor of 10 and most organic devices by a factor of $10^2$. Moreover, in contrast to other amorphous semiconductors, highly conducting degenerate states can be obtained with IGZO through doping, yet such a state cannot be produced with a-Si. IGZO thin films are capable of mobilities greaterthan 10 $cm^2$/Vs (higher than a-Si:H), and are transparent at visible wavelengths. For oxide semiconductors, carrier concentrations can be controlled through oxygen vacancy concentration. Hence, adjusting the oxygen partial pressure during deposition and post-deposition processing provides an effective method of controlling oxygen concentration. In this study, we deposited IGZO thinfilms at optimized conditions and then analyzed the film's electrical properties, surface morphology, and crystal structure. Then, we explored how to generate IGZO thin films using DC magnetron sputtering. We also describe the construction and characteristics of a bottom-gate-type TFT, including the output and transfer curves and bias stress instability mechanism.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1284-1287
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• 2007

Titanium dioxide ($TiO_2$) is promising candidate for fabricating blocking layer of gate dielectrics in non-volatile memory (NVM). In this work, we investigated $TiO_2$ as high dielectric constant material instead of silicon dioxide ($SiO_2$), which is generally used as blocking layer for NVM.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.267-270
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• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10$\mu\textrm{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sifted conventional LTIGBT and the conventional LTIGBT which has the width of 17$\mu\textrm{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17$\mu\textrm{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field in the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.81-82
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• 2006

SOI(Silicon-On-Insulator) MOSFET의 전기적 특성에 미치는 게이트 산화막과 계면준위 밀도의 관계를 조사하였다. 결함이 발생하지 않는 얕은 소스/드레인 접합을 형성하기 위하여 급속열처리를 이용한 고상확산방법으로 제작한 SOI MOSFET 소자는 급속열처리 과정에서 계면준위가 증가하여 소자의 특성이 열화된다. 이를 개선하기 위하여 $H_2/N_2$ 분위기에서 후속 열처리 공정을 함으로써 소자의 특성이 향상됨을 볼 수 있었다. 이와같이 급속열처리 공정과 $H_2/H_2$ 분위기에서의 후속 열처리 공정이 소자 특성에 미치는 영향을 분석하기 위하여 소자 시뮬레이션을 이용하여 게이트 산화막과 채널 사이의 계면준위 밀도를 분석하였다. 그 결과, n-MOSFET의 경우에는 acceptor-type trap, p-MOSFET의 경우에는 donor-type trap density가 소자특성에 큰 영향을 미치는 것을 확인하였다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.61.1-61.1
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• 2011

본 연구에서는 Zinc Tin Oxide (ZTO)/Ag/ZTO 다층 투명 전극을 제작하고 이를 비정질 ZTO (a-ZTO) 채널을 기반으로 한 TFT에 적용하여 투명 TFT의 전기적 특성을 확인하였다. 15${\times}$15 mm 크기의 ITO (gate)/Glass 기판상에 ALD법으로 투명 $Al_2O_3$절연층을 형성하고, RF sputtering법으로 50nm 두께의 a-ZTO 채널층을 형성하였다. 열처리를 위하여 Hot plate를 이용해 대기 중에서 $300^{\circ}C$의 온도로 20분간 열처리하여 채널 특성을 최적화 하였다. 이후 투명 Source/Drain으로 ZTO/Ag/ZTO 다층 투명 전극을 DC/RF sputtering법으로 패터닝하여 투명 TFT를 완성하였고, 평가를 위해 금속 (Mo)을 Source/Drain으로 사용한 TFT를 제작하여 그 성능을 비교하였다. ZTO/Ag/ZTO 다층 투명 전극은 Ag의 삽입으로 인하여 3.96ohm/square의 매우 낮은 면저항과 $3.24{\times}10-5ohm-cm$의 비저항을 나타내었으며, Antireflection 효과에 의해 가시광선 영역 (400~600 nm)에서 86.29%의 투과율을 나타내었다. ZTO/Ag/ZTO 다층 투명 전극 기반 투명 TFT는 $6.80cm^2/V-s$의 이동도와 $8.2{\times}10^6$의 $I_{ON}/I_{OFF}$비를 나타내어 금속 Source/Drain 전극에 준하는 특성을 나타내었다. 뿐만 아니라 전체 소자의 투과도 또한 ~73.26% 수준을 나타내어 투명 TFT용 Source/Drain 전극으로서 ZTO/Ag/ZTO 다층 투명 전극의 가능성을 확인하였다.

• 대한전자공학회논문지SD
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• 제38권3호
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• pp.155-165
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• 2001

2차원 소자 시뮬레이터를 사용하는 혼합모드 과도해석 방법을 제시하여, NMOS 트랜지스터를 ESD 보호용 소자로 사용하는 CMOS 칩에서의 충전소자모델(CDM) ESD 현상에 대한 분석을 시도하였다. 과도해석 결과의 분석을 통해 CDM 방전 경우 소자 파괴에 이르는 미케니즘에 대해 상세히 설명하였고 충전전기의 극성에 따른 방전 특성의 차이점도 비교 분석하였다. CDM 방전에서 가장 문제가 되는 입력버퍼의 게이트 산화막 파괴문제와 관련하여 배선저항 값의 변화에 의한 영향을 검토하였고, 입력버퍼회로 보호용 NMOS 트랜지스터의 추가에 의한 방전 특성의 변화에 대해 조사하였다.