• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.29 no.1
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• pp.191-195
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• 2005

The port entry system of the inner harbor in Pyeongtaek (Asan) was planned as lock-gate in 'Master plan project on port planning in Asan industry base(1990)', but was changed to tidal harbor in 'Project maintaining Master Plan for comprehensive development of Pyeongtaek (Asan) port(2001)'. Accordingly, southern sea bank constructed under the lower part of Seohae-bridge will be removed so that inbound/outbound vessels for the inner harbor can navigate at all times. However, in the view of the safety on passing through the lower of Seohae-bridge, navigating conditions for the inner harbor will be restricted in the single-way of 50,000 DWT vessel and the two-day of vessel less than 30,000 DWT. Therefore, this study carried out the estimation of traffic congestion arising from these vessels with above restrictions after supposing annual inbound/outboubd vessel's numbers for loading and unloading cargo surveyed on the inner harbor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1380-1386
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• 2009

In this paper, we propose a CQS(Calendar Queue Scheduler) architecture which was designed for processing multimedia and timing traffic in home network. With various characteristics of the increased traffic flowed in home such as VoIP, VOD, IPTV, and Best-efforts traffic, the needs of managing QoS(Quality of Service) are being discussed. Making a group regarding application or service is effective to guarantee successful QoS under the restricted circumstances. The proposed design is aimed for home gateway corresponding to the end points of receiver on end-to-end QoS and eligible for supporting multimedia traffic within restricted network sources and optimizing queue sizes. Then, we simulated the area for each module and each memory. The area for each module is referenced by NAND($2{\times}1$) Gate(11.09) when synthesizing with Magnachip 0.18 CMOS libraries through the Synopsys Design Compiler. We verified the portion of memory is 85.38% of the entire CQS. And each memory size is extracted through CACTI 5.3(a unit in mm2). According to the increase of the memory’sentry, the increment of memory area gradually increases, and defining the day size for 1 year definitely affects the total CQS area. In this paper, we discussed design methodology and operation for each module when designing CQS by hardware.

• The Journal of the Korean dental association
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• v.56 no.5
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• pp.263-276
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• 2018

Long-term survival and prognosis of narrow-diameter implants have been reported to be adequate to consider them a safe method for treating a deficient alveolar ridge. The objective of this study was to perform case report of narrow-diameter implants with a trapezoid-shape in anterior teeth alveolar bone. A 50-year-old male patient presented with discomfort due to mobility of all of the maxillary teeth and mandibular incisors. Due to destruction of alveolar bone, four anterior mandibular teeth were extracted. Soft tissue healing was allowed for approximately 3 months after the extraction, and a new design of implant placement was planned for the mandibular incisor area, followed by clinical and radiological evaluation. Implant placement was determined using an R2GATE surgical stent. The stability of the implants was assessed by ISQ measurements at the first and second implant surgery and after prosthetic placement. At 1 and 3 months and 1 year after implantation of the prosthesis, clinical and radiological examinations were performed. Another 50-year-old male patient presented with discomfort due to mobility of the mandibular central incisors. For the same reason as in the first patient, implant placement was carried out in the same way after extraction. ISQ measurements and clinical and radiological examinations were performed as in the previous case. In these two clinical cases, 12 months of follow-up revealed that the implant remained stable without inflammation or additional bone loss, and there was no discomfort to the patient. In conclusion, computer-guided implant surgery was used to place an implant in an optimal position considering the upper prosthesis. A new design of a narrow-diameter implant with a trapezoid-shape into anterior mandibular alveolar bone is a less invasive treatment method and is based on the contour of the deficient alveolar ridge. Through all of these procedures, we were able to reduce the number of traumas during surgery, reduce the operation time and total treatment period, and provide patients with more comfortable treatment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.71-79
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• 2010

This paper presents a design of a LLC resonant controller IC. LLC resonant controller IC controls the voltage of the 2nd side by adjusting frequency the input frequency of the external resonant circuit. The clock generator is integrated to provide the pulse to the resonant circuit and its frequency is controlled by the external resistor. Also, the frequency of the VCO is adjusted by the feedback voltage. The protection circuits such as UVLO(Under Voltage Lock Out), brown out, fault detector are implemented for the reliable and stable operation. The HVG, and LVG drivers can provide the high current and voltage to the IGBT. The designed LLC resonant controller IC is fabricated with the 0.35 um 2P3M BCD process. The overall die size is $1400um{\times}1450um$, and supply voltage is 5V, 15V.

• Journal of the Korean earth science society
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• v.21 no.2
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• pp.128-136
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• 2000

To understand the variation and transport pattern of suspended matters, salinity, tidal current and suspended matters in semiclosed Muan Bay have been monitored during winter and summer. The suspended matters show considerably seasonal variations with low concentration and homogeneity in the water column during winter season, but with high concentration and layering during summer season. Particularly, during summer season, the freshwater and the suspended matters influxed by the gate operation of the Youngsan River sea-dike are transported northward in accordance with the would flow into the inner-bay by relaxed flood currents after the construction of sea-dike and sea-walls in the Mokpo coastal zone. But, in the south bay-mouth, those matters outflow through the bay-mouth, resulting from tidal ebb dominance and asymmetry in the west bay-mouth. The residual suspended matter flux is much higher in the south bay-mouth(-0.0955kg/m ${\cdot}$ sec) than that of west bay-mouth(0.0078kg1m ${\cdot}$ sec). Accordingly, The Muan Bay is interpreted as erosion-dominated environments, and the erosion somewhat progresses in the intertidal flat of the bay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.111-121
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• 2012

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

• Magazine of the Korean Society of Agricultural Engineers
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• v.24 no.1
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• pp.44-52
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• 1982

Recently, estuary reserovoirs have been actively constructed in Korea and also in Japan there are a large number of estuary reservoirs constructed. But most of the estuary reservoirs are located at the downstream of a river where geographical condition is best for the construction of an enclosing dam. And an effective utilization of water from the estuary reservoir seems to be difficult even if estuary reservoirs are considered to be the water resources the most available for their watershed. Studies on estuary reservoirs so far have been mainly concentrated on the physical and engineering problems of the dam construction itself. The purpose of the present study is to review the estuary reservoir planning in connection with the water resources development and to study a basis of the planning. First, the levels of water use in Korea and Japan were compared with those of other countries in the world. And then, some representative reservoirs were selected to study the roles of a reservoir and water-using conditions in the watershed. Based on the study, a survey was given on the relation between a dam construction upstream and an estuary reservoir construction downstream of a river. Finally, a comprehensive examination was made of the bases of estuary reservoir planning. (1) The estuary reservoir planning is deeply related to the plan for water use develo- pment in the watershed. After the upstream water resources were fully developed up to the most, water reso- urces development by an estuary reservoir should be started. (2) If an estuary lake has a capacity big enough, it can store flood discharge of the watershed without any loss and become a basic facility that will bring about the maxi- mum use of water from the watershed. (3) Estuary reservoirs store water used in the upstream watershed, so recycling of water use is attained by the reservoir. Water in the estuary lake is difficult to be fresh water in its long run. Therefore, estuary reservoir should be located at a place where polluted water is purified and refused. All the planning should be based on the assumption that water in the estuary lake is not fresh but polluted after a long time. (4) The estuary lake can only supply water to the lower basin directly. But the upstream area is benefited from the estuary lake by exchange of irrigation water sources between the lower and the upper area. So a large-scale exchange plan between new and existing water resources is important. By constructing estuary reservoirs and the exchange of water sources between upper and lower areas, the reasonable maximum use of water from the whole watershed is at- tained. (5) The big problem coming from the water resources development by an enclosing estuary is salt water intrusion into the lake. To maintain the estuary lake salt-free, multi-purpose use of the lake should be avoided. It is necessary to take such fundamental measures as abolition of back flow operation of gate, and the closing of the fish port and the fish ladder. The results mentioned above were found in this study and these results of this study could be used for the adequate planning of estuary reservoirs in connection with the maximum water use of the watershed.