• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.148-150
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• 1993

The IGBT(Insulated Gate Bipolar Transistor) is a power semiconductor device that has gained acceptance among power electronic circuit design engineers for motor drive and Power converter applications. The device-circuit interaction of power insulated gate bipolar transistor for a series-inductor load, both with and without a snubber are, simulated. An analytical model for the transient operation of the IGBT is used in conjunction with the load circuit state equations for the simulations.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.365-366
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• 2008

한전 전력연구원이 주관하고 (주)효성이 참여하는 협동연구과제로 100MVA STATCOM(Static Compensator)개발이 수행 중에 있다. 100MVA STATCOM의 반도체 스위칭 소자로는 IGCT(Integrated Gate Commutated Thyristor)를 사용하고 있다. 본 논문에서는 IGCT GDU(Gate Drive Unit)전원공급장치인 HFI(High Frequency Inverter) 설계에 대하여 기술하고 있다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.303.1-303.1
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• 2014

좋은 전기적 특성을 가지면서 소자의 크기를 줄이기에 용이한 Gate-all-around (GAA) twin Si nanowire field-effect transistors (TSNWFETs)의 연구가 많이 진행되고 있다. Switching 특성과 단채널 효과가 없는 TSNWFETs의 특성은 GAA 구조의 본질적인 특성이다. TSNWFETs는 기존의 single Si nanowire TSNWFETs와 bulk FET에 비하여 Drive current가 nanowire의 지름에 많은 영향을 받지 않는다. 그러나 TSNWFETs의 전체 on-current는 훨씬 작고 nanowire의 지름이 작아지면서 줄어들게 되면서 소자의 sensing speed와 sensing margin 특성의 악화를 가지고 온다. GAA TSNWFETs의 제작 및 전기적 실험에 대한 연구는 많이 진행되었으나, GAA TSNWFETs의 전기적 특성에 대한 이론적 연구는 매우 적다. 본 연구에서는 GAA TSNWFETs의 nanowire 크기에 따른 전기적 특성을 관찰하였다. GAA TSNWFETs와 bulk FET의 전기적 특성을 양자역학을 고려하여 3차원 TCAD 시뮬레이션을 툴을 이용하여 계산하였다. GAA TSNWFETs와 bulk FET의 전류-전압 특성 계산을 통해 on-current 크기, subthreshold swing, drain-induced barrier lowering (DIBL), gate-induced drain leakage를 보았다. 전류가 흐르는 경로와 전기적 특성의 물리적 의미에 대한 연구를 위해 TSNWFETs에서의 전류 밀도, conduction band edge, potential 특성을 분석하였다. 시뮬레이션 결과를 통해 Switching 특성, 단채널 효과에 대한 면역 특성, nanowire의 단면적에 따른 전류 흐름을 보았다. nanowire의 크기가 작아지면서 DIBL이 증가하고 문턱전압과 전체 on-current는 감소하면서 소자의 특성이 악화된다. 이러한 결과는 GAA TSNWFETs의 전기적 특성을 이해하고 좋은 소자 특성을 위한 구조를 연구하는데 많은 도움이 될 것이다.

• Journal of Power Electronics
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• v.16 no.2
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.213-216
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• 2003

Recently a new high power device GCT (Gate Commutated Turn-off) thyristor has been successfully introduced to high power converting application areas. GCT thyristor has a quite different turn-off mechanism to the GTO thyristor. All main current during turn-off operation is commutated to the gate. Therefore, IGCT thyristor has many superior characteristics compared with GTO thyristor; especially, snubberless tum-off capacibility and higher turn-on capacibility. The basic structure of the GeT thyristor is same as that of the GTO thyristor. This makes the blocking voltage higher and controllable on-state current higher. The turn-off characteristic of the GCT thyristor is influenced by the minority carrier lifetime and the performance of the gate drive unit. In this paper, we present turn-off characteristics of the 2.5kV PT(Punch-Through) type GCT as a function of the minority carrier lifetime and variation of the doping profile shape of p-base region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.509-521
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• 1988

In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.627-630
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• 1991

This study is about vector controlled inverter for high quality elevator drive that is to improve the settling accuracy of elevator car and passenger's comfort in commercial buildings. In this study, an instantaneous space vector control type inverter was used to reduce the torque ripple ant to improve the velocity follow-up. This method calculates Instantaneous actual output torque and flux of induction motor by voltage and current, then compares them with a reference values by a speed regulator. The outputs of comparators select a switching mode, for an optimal voltage vector. Also, this study used IGBT (Insulated Gate Bipolar-Transistor), a high speed switching element, to reduce sound noise level, and DSP (Digital Signal Processor) was used to improve the reliability of the control circuit by fully digitalization.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1176-1178
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• 1992

This paper shows enhanced working performance of the battery fork-lift truck by developing the IGBT full bridge dc-dc convertor using one-chip micro-processor. The PWM pulse is generated from a 16 bit one-chip micro-processor for the speed control of DC motor. In order to ensure the operation of IGBT and motor pecewisely, IGBT gate drive circuit was designed by using current limiting IC and hige voltage limit IC. And also It is able to regenerative braking.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.58-69
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• 2016

This paper describes the design and implementation of a new diode clamped multilevel inverter for variable frequency drive. The diode clamp multilevel inverter has been widely used for low power, high voltage applications due to its superior performance. However, it has some limitations such as increased number of switching devices and complex PWM control. In this paper, a new topology is proposed. New topology requires only (N-1) switching devices and (N-3) clamping diodes compared to existing topology. A modified APO-PWM control method is used to generate gate pulses for inverter. The proposed inverter topology is coupled with single phase induction motor and its performance is tested by MATLAB simulation. Finally, a prototype model has built and its performance is tested with single phase variable frequency drive.