• Journal of Power Electronics
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• v.9 no.2
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• pp.259-266
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• 2009

In order to increase the power density of power converters, reduction of the switching losses at high-frequency switching conditions is one of the most important issues. This paper presents a new gate drive circuit that enables the reduction of switching losses in both the Power MOSFET and the IGBT. A distinctive feature of this method is that both the turn-on loss and the turn-off loss are decreased simultaneously without using a conventional ZVS circuit, such as the quasi-resonant adjunctive circuit. Experimental results of the switching loss of both the Power MOSFET and the IGBT are shown. In addition, an energy recovery circuit suitable for use in IGBTs that can be realized by modifying the proposed gate drive circuit is also proposed. The effectiveness of both the proposed circuits was confirmed experimentally by the buck-chopper circuit.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.120-126
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• 2006

A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the driver board can be reduced.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.713-717
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• 2001

This paper focuses on a network model for GCTs which can be used to investigate high power circuits with or without using RC-snubbers. The series connection of GCTs is commonly applied in the high power inverter field. Here expensive and space-consuming snubbers are applied, to overcome the problem of an asymmetric distribution of the blocking voltage among the single GCTs. As an alternative to large snubbers, a new active gate drive concept is proposed and investigated by simulation.

• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2213-2216
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• 1997

Efficient Switching of IGBT's requires fast gate drivers with high peak currents. This Paper will review the requirements for effient, reliable gate drive of IGBT's and behaviour of an IGBT switching chacteristcs. The purpose of the present paper is to investigate the switching loss mechanisms in IGBT such as MOSFETs in order to give a support to designers of IGBT gate drive circuits in selecting the more appropriate IGBTs to be used on the basics of design repuirements.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• 전자공학회논문지 IE
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• v.44 no.4
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• pp.30-34
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• 2007

The Channel environment is poor in the power line communication because power line proposed power supply use a communication medium. In this paper, we designed gate drive circuit used coupler reducing the signal diminution for the good communication. We analyzed receiving and transmitting operation of the coupler and designed the drive circuit with the suitable impedance. As a result, we improved the environment of impedance variation due to the inter reaction of many electron products. So, to improve BER(45%) enabled us to communicate smoothly in power line communication.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.2112-2114
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• 1998

A gate driver suitable for forced switch-mode power converters such as UPS and motor drive system is presented. The proposed gate driver uses regenerated snubber power and requires no separate power supply. This does not impose any additional complexity on the main switch. Experimental results show that the proposed circuit is valid.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.99-101
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• 2005

A gate driver with Boot-strap chain is proposed to drive Multi-level PDP sustain switches. The proposed gate driver uses only one boot-strap capacitor and one diode per each MOSFETs switch without floating power supply. By adoption of this gate driver circuits, the size, weight and the cost of the drivel board can be reduced.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2594-2596
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• 1999

Recently, white good market has interest with inverter product, which has merit to on/off type with respect to energy saving and noise. But, inverter product's cost is rising, because of adding inverter circuit component. To reduce cost, inverter gate drive trend is using HVIC which needs only single voltage. Also using HVIC, designer can compact PCB'size. This paper shows application technique and key point of designing HVIC