• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.579-582
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• 2009

This paper reports the electrical characteristics of polyvinylpyrrolidone (PVPy) and the performance of organic thin-film transistors with PVPy as a gate insulator. PVPy shows a dielectric constant of about 3 and contributes to the upright growth of pentacene molecules with 15.3${\AA}$ interplanar spacing. These results will be discussed.

• Transactions on Electrical and Electronic Materials
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• 제13권4호
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• pp.188-191
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• 2012

This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of $1{\times}10^{12}-1{\times}10^{14}/cm^2$ at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

• Journal of Information Display
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• 제9권4호
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• pp.35-38
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• 2008

This paper reports the electrical characteristics of polyvinylpyrrolidone (PVPy) and the performance of organic thin-film transistors (OTFTs) with PVPy as a gate insulator. PVPy shows a dielectric constant of about 3 and contributes to the upright growth of pentacene molecules with $15.3\AA$ interplanar spacing. OTFT with PVPy exhibited a field-effect mobility of 0.23 $cm^2$/Vs in the saturation regime and a threshold voltage of -12.7 V. It is notable that there was hardly any threshold voltage shift in the gate voltage sweep direction. Based on this reliable evidence, PVPy is proposed as a new gate insulator for reliable and high-performance OTFTs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.335-338
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• 1998

Ferroelectric Sr$_2$(Nb,Ta)$_2$O$_{7}$ (SNTO) thin films were prepared by chemical solution deposition processes. SNTO thin films were spin-coated on Pt/Ti/SiO$_2$/(100)Si substrates. After multiple coating, dried thin films were heat-treated for decomposition of residual organics and crystallization. B site-rich impurity phase, i.e. [Sr(Nb,Ta)$_2$O$_{6}$], was found after annealing, where its appearance was dependent on process temperature indicating the possible reaction with substrate. Dielectric and other relevant electrical properties were measured and the results showed a little possibility in ferroelectric gate random access memory devices.s.s.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.770-772
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• 2002

A new dry-processing method of organic gate dielectric film in field-effect transistors (FETs) was proposed. The method use vapor deposition polymerization (VDP) that is continuous and low temperature process. It has the advantages of shadow mask patterning and dry processing in flexible low-cost large area applications. Here, 80 nm-thick Al as a gate electrode was evaporated through shadow mask. Gate insulators used two different polyimides. The one material was 4,4'-oxydiphtahlic anhydride (ODPA) and 4,4'-oxydianiline (ODA). Another was 2,2-bis(3,4-dicarboxyphenyl) Hexafluoropropane Dianhydride (6FDA) and 4,4' -oxydianiline (ODA). These were co-deposited by high-vaccum thermal-evapora and cured at 150 $^{\circ}C$ for 1 hour, respectively. Pentacene as a semiconductor and 100 nm-thick Au as a source and drain electrode were evaporated through shadow mask.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.130-131
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• 2005

In the era of submicron devices, super ultra thin gate oxide characteristics are required. Titanium silicide process has studied gate oxide reliability and dielectric strength characteristics as the composition of gate electrode. In this study the author observed process characteristics on MOS structure. In view point of the process characteristics of MOS capacitor, the oxygen & Ti, Si2 was analyzed by SIMS analysis on before and after annealing with 1,2 step silicidation, the Ti contents[Count/sec]of $9.5{\times}1018$ & $6.5{\times}1018$ on before and after 2'nd anneal. The oxygen contents[Count/sec] of $4.3{\times}104$ & $3.65{\times}104$, the Si contents[Count/sec] of $4.2{\times}104$ & $3.7{\times}104$ on before and after 2'nd anneal. The rms value[A] was 4.98, & 4.03 on before and after 2'nd anneal.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.917-919
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• 2009

Effects of nano-silver contents(15~50wt%) on screen printed-etched gate electrodes and electrical characteristics of OTFTs were investigated. As Ag contents increased, the screen-printed film was transferred exactly without spreading and obtained the densely-packed layer with a stable and excellent conductivity but, its thickness was increased and surface became rougher. It was found that the leakage current of MIM devices and off-state currents of OTFTs became larger due to poor step coverage of PVP dielectric layer on the thick and rough gate electrodes for nano-Ag inks with Ag contents more than 30wt%.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.312-314
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• 2009

We have fabricated pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics. The gate dielectrics is composed of PVP, poly[melamine-coformaldehyde] (PMF) and photo-initiator [1-phenyl-2-hydroxy-2-methylpropane-1-one, Darocur1173]. By adding small amount (1 %) of photo-initiator, the cross-linking temperature is lowered to $115^{\circ}C$, which is lower than general thermal curing reaction temperature of cross-linked PVP (> $180^{\circ}C$). The hysteresis and the leakage current of the OTFTs are also decreased by adding the PMF and the photoinitiator in PVP gate dielectrics.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.100-106
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• 2010

The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.