• Journal of IKEEE
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• v.16 no.4
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• pp.283-289
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• 2012

In this paper, We proposed Separate Gate Technique(SGT) to improve the switching characteristics of Trench power MOSFET. Low gate-to-drain 전하 (Miller 전하 : Qgd) has to be achieved to improve the switching characteristics of Trench power MOSFET. A thin poly-silicon deposition is processed to form side wall which is used as gate and thus, it has thinner gate compared to the gate of conventional Trench MOSFET. The reduction of the overlapped area between the gate and the drain decreases the overlapped charge, and the performance of the proposed device is compared to the conventional Trench MOSFET using Silvaco T-CAD. Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) and Crss(reverse recovery capacitance : Cgd) are reduced to 14.3%, 23% and 30% respectively. To confirm the reduction effect of capacitance, the characteristics of inverter circuit is comprised. Consequently, the reverse recovery time is reduced by 28%. The proposed device can be fabricated with convetional processes without any electrical property degradation compare to conventional device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.10-15
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• 2008

In this paper, a new NMOS gate cross-connected current-mirror type bridge rectifier for UHF RFID applications is presented. The DC converting characteristics of the proposed rectifier are analyzed with the high frequency equivalent circuit and the gate capacitance reduction technique for reducing the gate leakage current due to the increasing of operating frequency is also proposed theoretically by circuitry method. As the results, the proposed rectifier shows nearly same DC output voltages as the existing NMOS gate cross-connected rectifier, but it shows the gate leakage current reduced to less than 1/4 and the power consumption reduced more than 30% at the load resistor, and it shows more stable DC supply voltages for the valiance of load resistance. In addition, the proposed rectifier shows high enough and well-rectified DC voltages for the frequency range of 13.56MHz HF(for ISO 18000-3), 915MHz UHF(for ISO 18000-6), and 2.45 GHz microwave(for ISO 18000-4). Therefore, the proposed rectifier can be used as a general purpose one to drive RFID transponder chips on various RFID systems which use specified frequencies.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.4
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• pp.1789-1796
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• 2012

In this paper, a new high-efficiency CMOS bridge rectifier for driving RFID tag chips is designed and analyzed. The input stage of the proposed rectifier is designed as a cascade structure connected with two NMOSs for reducing the gate capacitance by circuitry method, which is the main path of the leakage current that is increased when the operating frequency is increased. This gate capacitance reduction technique using the cascade input stage for reducing the gate leakage current is presented theoretically. The output characteristics of the proposed rectifier are derived analytically using its high frequency small-signal equivalent circuit. For the general load resistance of $50K{\Omega}$, the proposed rectifier shows better power conversion efficiencies of 28.9% for 915MHz UHF (for ISO 18000 -6) and 15.3% for 2.45GHz microwave (for ISO 18000-4) than those of 26.3% and 26.8% for 915MHz, and 13.2% and 12.6% for 2.45GHz of compared other two existing rectifiers. Therefore, the proposed rectifier may be used as a general purpose rectifier to drive tag chips for various RFID systems.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.6
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• pp.1095-1102
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• 2010

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. High growth of the flash memory market has been driven by two combined technological efforts that are an aggressive scaling technique which doubles the memory density every year and the introduction of MLC(multi level cell) technology. Therefore, the CCI is a critical factor which affects occurring data errors in cells. We introduced an equation of CCI model and designed an equalizer reducing CCI based on the proposed equation. In the model, we have been considered the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. Also we design and verify the proposed equalizer using Matlab. As the simulation result, the error correction ratio of the equalizer shows about 20% under 20nm NAND process where the memory channel model has serious CCI.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.29-35
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• 2004

Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.