• The Journal of the Convergence on Culture Technology
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• v.9 no.6
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• pp.957-966
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• 2023

In this paper, we propose a new real-time adaptive PID temperature control technique. This is a technique that prevents overshoot by introducing a model that represents the control object. To prevent excessive integration that causes overshoot, integral control adjusts the integral gain to track the heat loss of the model in real time. In the conventional PID control, the integration was dependent on proportional control and the gain was fixed to a constant. As a result, applying two gains that mismatch each other could cause excessive overshoot. However, the proposed adaptive control actively eliminates overshoot so that the integral control amount does not always exceed the heat loss. The cause of overshoot in PID control is integration. Basically, proportional control does not cause overshoot. Therefore, according to the proposed technique, adaptive PID control without the need for tuning experiments can be realized.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.1029-1034
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• 2010

For All Digital QPSK receivers, a phase recovery scheme is required to fix the arbitrarily rotated I/Q quadrature signals due to the transmission path and clock mismatch between the transmitter and the receiver. The conventional Costas phase recovery loop scheme requires a separate AGC(Automatic Gain Control) to obtain the performance independent of input signal power. This paper proposes a simple scheme which separates the phase and amplitude of the input signal via CORDIC algorithm and performs the phase recovery and amplitude compensation simultaneously. The proposed scheme can considerably reduce the logic resources in hardware implementation, has been verified by C++ and Model Sim simulations.

• ETRI Journal
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• v.36 no.3
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• pp.510-513
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• 2014

A Q-band pHEMT image-rejection low-noise amplifier (IR-LNA) is presented using inter-stage tunable resonators. The inter-stage L-C resonators can maximize an image rejection by functioning as inter-stage matching circuits at an operating frequency ($F_{OP}$) and short circuits at an image frequency ($F_{IM}$). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L-C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR-LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and $F_{IM}/F_{OP}$ of the reported millimeter/quasi-millimeter wave IR-LNAs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1685-1691
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• 2004

The objective of this study is aimed at reducing the contour error of AC Servo derives by improving the interpolation error of each axis through variable structure control system. The errors in machining process by AC Servo motor are due to many elements, such as the delay of the servo drivers, friction and the gain mismatch between x axis and y axis motors and so on. Sliding mode control system is applied to a AC servo drive as a numerical example in this paper. The experiment results which are compared with those of typical PI scheme show the validity of improvement in circular interpolation error of the system.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.165-170
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• 2014

Speech enhancement techniques that remove surrounding noise are stressed to preprocessor of speech recognition. Among the various speech enhancement techniques, Codebook-based Speech Enhancement (CBSE) operates efficiently in non-stationary noise environments. But, CBSE has some problems that inaccurate gains can be estimated if mismatch occur between input noisy signal and trained speech/noise codevectors. In this paper, the Normalized Weighting Factor (NWF) is calculated by long-term noise estimation algorithm based on Signal-to-Noise Ratio, compensated to the conventional inaccurate gains. The proposed CBSE shows better performance than conventional CBSE.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.10 no.5
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• pp.1-6
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• 2011

Machine tool errors have to be characterized and predicted to improve machine tool accuracy. Therefore, it is very important to assess errors in machine tools. Volumetric error analysis has been developed by many researchers. This paper presents a useful technique for analyzing the volumetric errors in machine tools using the ball bar. The volumetric error model is proposed in specific vertical machining center and the program is developed for generating NC code, acquiring the ball bar data, and analyzing the volumetric errors. The developed system assesses the volumetric errors such as positional, straightness, squareness, and back lash. Also this system analyzes the dynamic performance such as servo gain mismatch. The radial data acquired by ball bar on 3D space is used for analyzing these errors. It is convenient to test the volumetric errors on 3D space because all errors are calculated at once. The developed system has been tested using an actual vertical machining center.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.8
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• pp.857-864
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• 2010

In this paper, we analyse the effect of the path imbalances(gain and phase mismatches) in LINC(LInear amplification with Nonlinear Component) system, and propose a simple scheme using LUTs(Look Up Table) to compensate the path imbalances. The EVM(Error Vector Magnitude) and ACPR(Adjacent Channel Power Ratio) of the LINC system are degraded significantly by the path imbalances because it adopts an outphasing technique. The EVM and ACPR are theoretically extracted for two variables(gain and phase mismatch factors) and 2-D LUTs for those are generated based on the analysis. The efficient and simple compensation scheme for the path imbalances is proposed using the 2-D LUTs. A LINC system with the suggested compensation scheme is implemented, and the proposed method is verified with an experiment. A 16-QAM signal with 1.5 MHz bandwidth is used. Before the compensation, the path gain ratio was 95 % and phase error was $19.33^{\circ}$. The proposed scheme adjusts those values with 99 % and $0.5^{\circ}$, and improves ACPR about 18.1 dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.