• Magazine of the Korean Society of Agricultural Engineers
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• v.36 no.4
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• pp.33-38
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• 1994

Floating-type automatic turnout was developed for the purpose of reducing labor cost and labor-working hours related to turnout management. The point of automation is to use a flexible-float within the turnout. The weight of float is changed by emptying and filling with water at the beginning and ending of irrigation. The turnout is controlled to open and close small bole on the float bottom using electromagnets. With the weight control of float. the gate of turnout is opened by the empty float to begin irrigatiom and is closed by the filled float to stop irrigation. The turnout was designed to be operated by the main computer and to minimize electric power consumption by sending an electric current at the beginning and ending of irrigation. The functional experiment was succesfully carried out and the rating curves for both free overflow condition and submerged flow condition were derived.

• Journal of architectural history
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• v.27 no.4
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• pp.7-16
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• 2018

This study is focusing on anchogongs(按草工) in yeonggeonuigwes(營建儀軌), which were recorded with few details and in unsettled transcriptions. First, the positions and functions of anchogongs in $18^{th}$ censtury are analyzed by comparing to anchogongs in more detailed early $19^{th}$ century yeonggeonuigwes and those in extant buildings. Second, with the result, the historical significances are presumed in changing transcriptions of anchogong terms in those uigwes. In $18^{th}$ century uigwes, most of anchogongs are functioned as matbo-anchogongs and only four anchogongs in a gate building were used as jongryang-anchogongs. It is mainly because the sorts of buildings in $18^{th}$ century yeonggeonuigwes had only several varieties: most of the buildings belonging royal shrines. Transcriptions of anchogong terms had been changed for reflecting functional developments of anchogongs in $18^{th}$ century. However, reflections were much later than changes of actual functions.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.1-9
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• 1994

This paper analyzes the faults and their mechanism of CMOS ICs using IDDQ testing technique and evalutes the reliability of the chips that fail this test. It is implemented by the three testing phases, initial test, burn-in and life test. Each testing phase includes the parametric test, functional test, IDDQ test and propagation delay test. It is shown that the short faults such as gate-oxide short, bridging can be only detected by IDDQ testing technique and the number of test patterns for this test technique is very few. After first burn-in, the IDDQ of some test chips is decreased, which is increased in conventional studies and in subsequent burn-in, the IDDQ of all test chips is stabilized. It is verified that the resistive short faults exist in the test chips and it is deteriorated with time and causes the logic fault. Also, the new testing technique which can easily detect the rsistive short fault is proposed.

• Journal of IKEEE
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• v.18 no.4
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• pp.566-571
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• 2014

A safety class field programmable gate array based system in nuclear power plant has been developed to improve the diversity. Testbench is necessary to satisfy the technical reference, IEC-62566, for verification and validation of register transfer level code. We use the open verification methodology(OVM) developed by standard body. We show that our testbench can use random input for test. And also we show that reusability of block level testbench for the integration level testbench, which is very efficient for large scale system like nuclear reactor protection system.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.56-58
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• 2005

To illustrate an application of the field effect transistor (FET) structure, this study suggests a new cantilever, using atomic force microscopy (AFM), for sensing surface potentials in nanoscale. A combination of the micro-electromechanical system technique for surface and bulk and the complementary metal oxide semiconductor process has been employed to fabricate the cantilever with a silicon-on-insulator (SOI) wafer. After the implantation of a high-ion dose, thermal annealing was used to control the channel length between the source and the drain. The basic principle of this cantilever is similar to the FET without a gate electrode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1433-1442
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• 1998

The thesis presents a dual audio decoder which can decode both AC-3 and MPEG-2 bitstream. The MPEG-2 synthesis processi s optimized via FFT to establish the common data path with AC-'3s. A dual audio decoder consists of a DSP core which performs the control-intensive part of each algorithm and a common synthesis filter which perfomrs the computation-intensive part. All the components of the dual audio decoder have been described in VHDL and simulated with a SYNOPSYS tool. The software modeling of the DSP core was used for functional validation. After being synthesized using 0.6 .mu.m-3ML technology standard cell, the dual audio decoder was simulated at gate-level with a COMPASS tool for hardware validation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.12
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• pp.708-716
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• 2003

The surface EMG signal detected from voluntarily activated muscles can be used as a control signal for functional electrical stimulation. To use the voluntary EMG signal, it is necessary to eliminate the muscle response evoked by the electrical stimulation and enable to process the algorithm in real time. In this paper, we propose the Gram-Schmidt(GS) algorithm and implement it in FPGA(field programmable gate array). GS algorithm is efficient to eliminate periodic signals like muscle response, and is more stable and suitable to FPGA implementations than the conventional least-square approach, due to the systolic array structure.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• Journal of Navigation and Port Research
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• v.31 no.3 s.119
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• pp.205-212
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• 2007

Due to the construction of Incheon Grand Bridge, there is driven a necessity for rearranging the function of Inner Port with the development of Outer South Port. In this paper, I'd like to simulate the port operation levels of Lock Gate in Inner Port with estimating the traffic volumes of 2011 and 2015, which will reveal the Demurrage Cost and the Accumulation Cost of Freight in Inner Port. Finally I will evaluate the economic movement effects of the container ship's calling from Inner port to South Port/Outer South Port from 2011 to 2015. The results are as followings ; (1) The average utilization of Lock Gates are reduced by $7\sim8$ percentage point. (2) The mean queueing value are saved by 25 percentage point. (3) The Demurrage Cost and the Accumulation Cost of Freight except Lock Gate charges and the Benefit of Routeing Reduction are saved about 800 million Won annually.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.281.1-281.1
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• 2016

Transition metal dichalcogenides (TMDCs) are promising layered structure materials for next-generation nano electronic devices. Many investigation on the FET device using TMDCs channel material have been performed with some integrated approach. To use TMDCs for channel material of top-gate thin film transistor(TFT), the study on high-k dielectrics on TMDCs is necessary. However, uniform growth of atomic-layer-deposited high-k dielectric film on TMDCs is difficult, owing to the lack of dangling bonds and functional groups on TMDC's basal plane. We demonstrate the effect of remote oxygen plasma pretreatment of large area synthesized few-layer MoSe2 on the growth behavior of Al2O3, which were formed by atomic layer deposition (ALD) using tri-methylaluminum (TMA) metal precursors with water oxidant. We investigated uniformity of Al2O3 by Atomic force microscopy (AFM) and Scanning electron microscopy (SEM). Raman features of MoSe2 with remote plasma pretreatment time were obtained to confirm physical plasma damage. In addition, X-ray photoelectron spectroscopy (XPS) was measured to investigate the reaction between MoSe2 and oxygen atom after the remote O2 plasma pretreatment. Finally, we have uniform Al2O3 thin film on the MoSe2 by remote O2 plasma pretreatment before ALD. This study can provide interfacial engineering process to decrease the leakage current and to improve mobility of top-gate TFT much higher.