• Nuclear Engineering and Technology
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• v.54 no.11
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• pp.4220-4225
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• 2022

Monte Carlo (MC) simulations are increasingly being used as an alternative or supplement to the gamma spectrometric method in determining the full energy peak efficiency (FEPE) necessary for radionuclide identification and quantification. The MC method is more advantageous than the experimental method in terms of both cost and time. Experimental calibration with standard sources is difficult, especially for specimens with unusually shaped geometries. However, with MC, efficiency values can be obtained by modeling the geometry as desired without using any calibration source. Modeling the detector with the correct parameters is critical in the MC method. These parameters given to the user by the manufacturer are especially the dimensions of the crystal and its front edge, the thickness of the dead layer, dimensions, and materials of the detector components. This study aimed to investigate the effect of the front edge geometry of the detector crystal on efficiency, so the effect of rounded and sharp modeled front edges on the FEPE was investigated for <300 keV with three different HPGe detectors in point and volume source geometries using PHITS MC code. All results showed that the crystal should be modeled as a rounded edge, especially for gamma-ray energies below 100 keV.

• Journal of the Korea Society of Computer and Information
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• v.24 no.3
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• pp.29-39
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• 2019

In this study, we introduce a model that satisfies energy efficiency and economical efficiency by introducing and demonstrating cogeneration generators in industrial complexes using various actual data collected at the site. The proposed model is composed of three scenarios, ie, full - time operation, scenario operated according to demand, and a fusion type. In this study, the power generation profit and surplus thermal energy are measured according to the operation of the generator, and the thermal energy is traded according to the demand of the customer to calculate the profit and loss including the heat and evaluate the economic efficiency. As a result of the study, it is relatively profitable to reduce the generation of the generator under the condition that the electricity rate is low and the gas rate is high, while the basic charge is not increased. On the contrary, if the electricity rate is high and the gas rate is low, The more you start up, the more profit you can see. These results show that even a cogeneration power plant with a low economic efficiency due to a low "spark spread" has sufficient economic value if it can sell more than a certain amount of heat energy from a nearby customer and adjust the applied power through peak management.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.364-367
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• 2001

ZVS Full-bridge converter is widely used in medium power level(1-3kW). ZVS can be designed within a limited load range and ZVS failure at light load condition is assumed to be acceptable within the given efficiency and thermal constraints. However, unbalanced ZVS resonant energy caused by dc blocking capacitor may alleviate the switching loss problem at light load condition. ZVS resonant energy is unbalanced by do blocking capacitor. This problem causes loss and heat concentration of a switch leg, In this paper, this problem is analyzed, and a novel control method is proposed to solve the problem.

• Nuclear Engineering and Technology
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• v.56 no.6
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• pp.2120-2130
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• 2024

This study significantly reduced the seismic analysis time of PCSG assembly by introducing a reduced model using homogenization and sub-structuring methods. The homogenization method was applied to the primary and secondary micro-channel sheets, and the sub-structuring method was applied to the PCSG module sets. Modal analysis and frequency response analysis were then performed to validate the accuracy of the reduced model. The analysis results were compared with the full model and it was confirmed that the reduced model provided almost the same analysis results as the full model. To verify the computational efficiency of the reduced model, the computational time was then compared with the full model, and it was confirmed that the modal analysis time was reduced by 3.42 times and the frequency response analysis time was reduced by 4.59 times.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.255-260
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• 2016

In this paper, a full-wave rectifier (FWR) with a simple vibration detector suitable for use with vibrational energy harvesting systems is presented. Conventional active FWRs where active diodes are used to reduce the diode voltage drop and increase the system efficiency are usually powered from the output. Output-powered FWRs exhibit relatively high efficiencies because the comparators used in active diodes are powered from the stable output voltage. Nevertheless, a major drawback is that these FWRs consume power from the output storage capacitor even when the system is not harvesting any energy. To overcome the problem, a technique using a simple vibration detector consisting of a peak detector and a level converter is proposed. The vibration detector detects whether vibrational energy exists or not in the input terminal and disables the comparators when there is no vibrational energy. The proposed FWR with the vibration detector is designed using a $0.35-{\mu}m$ CMOS process. Simulation results have verified the effectiveness of the proposed scheme. By using the proposed vibration detector, a decrease in leakage current by approximately 67,000 times can be achieved after the vibration disappears.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.278-281
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• 2014

This paper presents the performance comparison of three types of full-wave rectifiers for vibration energy harvesting. The first rectifier is consisted of two active diodes and two MOSFETs, and the comparators of the active diodes are powered from the output of the rectifier. The second one is a 2-stage full-wave rectifier. It comprises the basic rectifier consisted of four MOSFETs and an active diode. The comparator is also powered from the output of the rectifier. The third one is an input powered rectifier. It has the same structure as the second rectifier, but the comparator is powered from the input of the rectifier. These rectifiers have been designed using a 0.35um CMOS process and their performances have been compared through simulations. In terms of efficiency, the first rectifier shows the best performance at heavy loads, but the second one is suitable at light loads. When the power consumption during absence of vibration is more important than efficiency, the input-powered rectifier is proper.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.179-185
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• 2005

This paper presents a novel circuit topology of a high efficiency single-phase power conditioner. This power conditioner is composed of time-sharing sinewave absolute pulse width modulated boost chopper with a bypass diode in the first power processing stage and time-sharing sinewave pulse width modulated full-bridge inverter in the second power processing stage operated by time-sharing dual mode pulse pattern control scheme. The unique operating principle of the two power processing stage with time-sharing dual mode sinewave modulation scheme is described with a design example. This paper proposes also a sinewave tracking voltage controlled soft switching PWM boost chopper with a passive auxiliary edge-resonant snubber. The new conceptual operating principle of this novel power conditioner related to new energy utilization system is presented and discussed through the experimental results.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.395-398
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• 2005

A novel full-bridge converter with a new energy-recovery driver implemented a regenerative transformer is proposed to improve the efficiency for wide input voltage range and load variation. The main switches achieve ZVS independent of the load current condition. During the free wheeling period, conduction loss is minimized by recovering the circulating energy to the source. The principle of operation, design consideration and experimental result, including efficiency, are presented in the case of large variation of the input voltage or load. A proposed 1kW converter prototype is compared with a PS-FB converter.

• Journal of Information Technology Services
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• v.14 no.3
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• pp.183-196
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• 2015

The concept of energy-efficient networking has begun to spread in the past few years, gaining increasing popularity. A common opinion among networking researchers is that the sole introduction of low consumption silicon technologies may not be enough to effectively curb energy requirements. Thus, for disruptively boosting the network energy efficiency, these hardware enhancements must be integrated with ad-hoc mechanisms that explicitly manage energy saving, by exploiting network-specific features. The IEEE 802.3az Energy Efficient Ethernet (EEE) standard is one of such efforts. EEE introduces a low power mode for the most common Ethernet physical layer standards and is expected to provide large energy savings. However, it has been shown that EEE may not achieve good energy efficiency because mode transition overheads can be significant, leading to almost full energy consumption even at low utilization levels. Coalescing techniques such as packet coalescing and interrupt coalescing were proposed to improve energy efficiency of EEE, but their implementations typically adopt a simple policy that employs a few fixed values for coalescing parameters, thus it is difficult to achieve optimal energy efficiency. The paper proposes adaptive interrupt coalescing (AIC) that adopts an optimal policy that could not only improve energy efficiency but support performance. AIC has been implemented at the sender side with the Intel 82579 network interface card (NIC) and e1000e Linux device driver. The experiments were performed at 100 M bps transfer rate and show that energy efficiency of AIC is improved in most cases despite performance consideration and in the best case can be improved up to 37% compared to that of conventional interrupt coalescing techniques.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.9
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• pp.1239-1248
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• 2018

This paper proposes a fault tolerant and high efficiency operation algorithm for a 4 LEG DC/DC converter for a battery energy storage system(BESS) forming a main power source in a standalone DC micro grid. The BESS for the main power supply in the stand-alone DC micro-grid is required to operate at high speed according to fault tolerant control and load by operating at all times. Fault-tolerance control changes the short-circuit fault to an open-circuit fault by using a fuse in case of leg fault in 4 legs, and operates stably through phase shift control. In addition, considering the loss of the power semiconductor, the number of LEG operation is adjusted to operate at high efficiency in the full load region. In this paper, fault tolerant control and high efficiency operation algorithm of DC/DC converter for BESS in standalone DC micro grid is presented and it is proved through simulation and experiment.