• Journal of Animal Environmental Science
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• v.15 no.3
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• pp.251-262
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• 2009

In this research dairy cattle barn facilities what are 4,198 houses hold over 50 heads were surveyed by scale and province. Full-time farms hold over 50 heads breed total 344,514 heads. Each of Farms holds 50 to 99 heads were 79.8 percent and breed average 82.1 heads. Dairy cattle barns were constructed september 1995 averagely. Each of barns have $1,740.0\;m^2$ scale. The construction type of dairy cattle barn was almost litter barn type 84.0%, freestyle type 5.1%, mooring+litter ground type 17.3% and other types 4.4%. The litter barn type was popular in small farms. But in large farms, freestyle type was popular than small farms. The construction type of dairy cattle barn was almost litter barn type 84.0%, freestyle type 5.1%, moohng+ltter ground type 17.3% and other types 4.4%. Type of dairy cattle robotic milking system was pipeline 41.5%, herringbone 22.8% and tandem 35.8%. The pipeline type was popular in small farms which have 50~99 heads. But in large farms which have over 200 heads, tandem type was popular than small farms. Proportion of floor type of dairy cattle barn was almost litter type 94.9%. Scraper type was popular in large farms than in small farms. Proportion of roof type of dairy cattle barn was slate 32.5%, vinyl 16.3%, sunlight 11.1%, panel 10.9, zinc plate 8.8 and steel plate 8.3%. Roof type was lots of slate type before 1995. But vinyl type is increasing after 1995. Proportion of wall type of dairy cattle barn was almost open type 83.3% and winch-curtain 26.8%. Utilization period of dairy cattle barn was 9.2 years about milker, 7.9 years about automatic feeder, 9.2 years about waterer and 10.4 years about electric facilities. In this results, there were lots of improvements about automatic feeder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.43-53
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• 2010

Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.

• Journal of the Korean Institute of Gas
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• v.16 no.1
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• pp.15-21
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• 2012

An analysis was completed of the hazards distance of hydrogen accidents such as jet release, jet fire, and vapor cloud explosion(VCE) of hydrogen gas, and simplified equations have been proposed to predict the hazard distances to set up safety distance by the gas dispersion, fire, and explosion following hydrogen gas release. For a small release rate of hydrogen gas, such as from a pine-hole, the hazard distance from jet dispersion is longer than that from jet fire. The hazard distance is directly proportional to the pressure raised to a half power and to the diameter of hole and up to several tens meters. For a large release rate, such as from full bore rupture of a pipeline or a large hole of storage vessel, the hazard distance from a large jet fire is longer than that from unconfined vapor cloud explosion. The hazard distance from the fire may be up to several hundred meters. Hydrogen filling station in urban area is difficult to compliance with the safety distance criterion, if the accident scenario of large hydrogen gas release is basis for setting up the safety distance, which is minimum separation distance between the station and building. Therefore, the accident of large hydrogen gas release must be prevented by using safety devices and the safety distance may be set based on the small release rate of hydrogen gas. But if there are any possibility of large release, populated building, such as school, hospital etc, should be separated several hundred meters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• Journal of Korea Entertainment Industry Association
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• v.15 no.1
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• pp.53-62
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• 2021

After the first to present projected moving pictures to audiences, the film industry has been reshaping along with technological advancements. Through the full-scale introduction of visual effects-oriented post-production and digital technologies in the film-making process, the film industry has not only undergone significant changes in the production, but is also embracing the cutting edge technologies broadly and expanding the scope of industry. Not long after the change to digital cinema, the concept of artificial intelligence, first known at the Dartmouth summer research project in 1956, before the digitalization of film, is expected to bring about a big transformation in the film industry once again. Large volume of clear digital data from digital film-making makes easy to apply recent artificial intelligence technologies represented by machine learning and deep learning. The use of artificial intelligence techniques is prominent around major visual effects studios due to automate many laborious, time-consuming tasks currently performed by artists. This study aims to predict how artificial intelligence technology will change the film industry in the future through analysis of visual effects production cases using artificial intelligence technology as a production tool and to discuss the industrial potential of artificial intelligence as visual effects technology.

• Journal of Advanced Information Technology and Convergence
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• v.9 no.1
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• pp.115-125
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• 2019

In this paper, the image is received from the camera and the lane is sensed. There are various ways to detect lanes. Generally, the method of detecting edges uses a lot of the Sobel edge detection and the Canny edge detection. The minimum use of multiplication and division is used when designing for the hardware configuration. The images are tested using a black box image mounted on the vehicle. Because the top of the image of the used the black box is mostly background, the calculation process is excluded. Also, to speed up, YCbCr is calculated from the image and only the data for the desired color, white and yellow lane, is obtained to detect the lane. The median filter is used to remove noise from images. Intermediate filters excel at noise rejection, but they generally take a long time to compare all values. In this paper, by using addition, the time can be shortened by obtaining and using the result value of the median filter. In case of the Sobel edge detection, the speed is faster and noise sensitive compared to the Canny edge detection. These shortcomings are constructed using complementary algorithms. It also organizes and processes data into parallel processing pipelines. To reduce the size of memory, the system does not use memory to store all data at each step, but stores it using four line buffers. Three line buffers perform mask operations, and one line buffer stores new data at the same time as the operation. Through this work, memory can use six times faster the processing speed and about 33% greater quantity than other methods presented in this paper. The target operating frequency is designed so that the system operates at 50MHz. It is possible to use 2157fps for the images of 640by360 size based on the target operating frequency, 540fps for the HD images and 240fps for the Full HD images, which can be used for most images with 30fps as well as 60fps for the images with 60fps. The maximum operating frequency can be used for larger amounts of the frame processing.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}