• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.323-329
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• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• Journal of Plant Biotechnology
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• v.35 no.1
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• pp.47-53
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• 2008

Effects of growth regulators and culture conditions on seed germination, haustorium development, and callus formation of Korean mistletoe (Viscum album var. coloratum (Kom.) Ohwi) were described. Histological examination showed that seed of V. album contained one or two zygotic embryos with rod shape, and actively dividing cells were mainly distributed in radicle region rather than cotyledon of zygotic embryo. The most significant factor for seed germination and haustorium development of V. album was the requirement of the light. Various growth regulators examined in this study failed to substitute the effect of the light on seed germination. The frequency of callus formation was highest at 27.3% when flower buds were cultured onto B5 medium containing $0.1\;mgl^{-1}$ IAA. Explants from other organs were recalcitrant in forming calluses. Culture conditions described in this study could be applied for production of useful metabolites and multiplication of V. album in future.

• Journal of Broadcast Engineering
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• v.4 no.2
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• pp.144-154
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• 1999

The binomial sequences are family of orthogonal sequences that can be generated with remarkable simplicity-no multiplications are necessary. This paper introduces a class of non-recursive multidimensional filters for frequency-selective image processing without multiplication operations. The magnitude responses are narrow-band. approximately gaussian-shaped with center frequencies which can be positioned to yield low-pass. band-pass. or high-pass filtering. Algorithms for the efficient implementation of these filters in software or in hardware are described. Also. we show that the binomial QMFs are the maximally flat magnitude square Perfect Reconstruction paraunitary filters with good compression capability and these are shown to be wavelet filters as well. In wavelet transform the original image is decomposed at different scales using a pyramidal algorithm architecture. The decomposition is along the vertical and horizontal direction and maintains constant the number of pixels required to describe the images. An efficient perfect reconstruction binomial QMF-Wavelet signal decomposition structure is proposed. The technique provides a set of filter solutions with very good amplitude responses and band split. The proposed binomial QMF-filter structure is efficient, simple to implement on VLSl. and suitable for multi-resolution signal decomposition and coding applications.

• Journal of Plant Biotechnology
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• v.30 no.1
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• pp.59-63
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• 2003

This experiment was conducted to propagate Zantedeschia spp. in vitro. The frequency of adventitious bud clusters (ABC) formation from shoot tips in Z. 'Best Gold' was high at more than 65% on media with 2.0∼5.0 mg/L BA or 0.1∼1.0 mg/L thidiazuron. The highest formation rate of ABC (75%) was obtained on medium containing 2.0 mg/L BA. Comparing to treatment of BA alone, combined one of BA and NAA did not stimulate the formation of ABC and the shoot regeneration from shoot tips. The proliferation of ABC from sections (0.7∼1.0 cm) of ABC occurred effective on medium with 2.0 mg/L BA. Shoots developed from the sections (0.7∼1.0 cm) of ABC grew and rooted favorably on media containing 1.0∼2,0 mg/L IBA. The shoots were multiplicated effectively on medium with 0.5 mg/L thidiazuron in Z. 'Childsiana', on medium with 3.0 mg/L BA in 2. 'Golden Affair', and on medium with 5.0∼10.0 mg/L BA in Z. 'Pacific Pink'.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• The KIPS Transactions:PartC
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• v.15C no.2
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• pp.133-140
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• 2008

In this paper, we propose a high performance elliptic curve cryptographic processor over $GF(2^{163})$. The proposed architecture is based on a modified Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for $GF(2^{163})$ field arithmetic. To achieve a high throughput rates, we design two new word-level arithmetic units over $GF(2^{163})$ and derive a parallelized elliptic curve point doubling and point addition algorithm with uniform addressing based on the Lopez-Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143MHz. Our design is roughly 4.8 times faster with 2 times increased hardware complexity compared with the previous hardware implementation proposed by Shu. et. al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2052-2058
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• 2009

As the operating frequency of digital system increases and voltage swing decreases, an accurate and high speed analysis of PCB board becomes very important. Transmission matrix method, which use the multiple products of unit column matrix, is the highest speedy method in PCB board analysis. In this paper a new method to reduce the calculation time of PCB board impedances is proposed. First, in this method the eigenvalue and eigenvectors of the transmission matrix for unit column of PCB are calculated and the transmission matrix for the unit column is transformed using similarity transform to reduce the number of multiplication on the matrix elements. This method using the similarity transform can reduce the calculation time greatly comparing the previous method. The proposed method is applied to the 1.3 inch by 1.9 inch board and shows about 10 times reduction of calculation time. This method can be applied to the PCB design which needs a lots of repetitive calculation of board impedances.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1484-1489
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• 2004

Given a video frame in terms of its 8${\times}$8 block-DCT coefncients, we wish to obtain a downsized or upsized version of this Dame also in terms of 8${\times}$8 block DCT coefficients. The DCT being a linear unitary transform is distributive over matrix multiplication. This fact has been used for downsampling video frames in the DCT domains in Dugad's, Mukherjee's, and Park's methods. The downsampling and upsampling schemes combined together preserve all the low-frequency DCT coefficients of the original image. This implies tremendous savings for coding the difference between the original frame (unsampled image) and its prediction (the upsampled image).This is desirable for many applications based on scalable encoding of video. In this paper, we extend the earlier works to various DCT sizes, when we downsample and then upsample of an image by a factor of two. Through experiment, we could improve the PSM values whenever we increase the DCT block size. However, because the complexity will be also increase, we can say there is a tradeoff. The experiment result would provide important data for developing fast algorithms of compressed-domain image/video resizing.