• Bulletin of the Korean Chemical Society
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• v.34 no.2
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• pp.447-452
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• 2013

In this study we report a new method for the synthesis of a silica monolithic column bed with bimodal pores (throughpores and mesopores). The template induced synthesis method was used to direct bimodal pores simultaneously instead of the usual post base-treating method. Block polymer Pluronic F127 was chosen as a dual-function template to form hierarchically porous silica monolith with both macropores and mesopores. This is a simplification of the method of monolithic column preparation. Poly(ethylene glycol) was used as a partial substitute for F127 can effectively prevent shrinkage during the monolith aging process without losing much surface area (944 $m^2/g$ to 807 $m^2/g$). More importantly, the resultant material showed a much narrower mesopore size (centered at 6 nm) distribution than that made using only F127 as the template reagent, which helps the mass transfer process. The solvent washing method was used to remove the remaining organic template, and it was proved to be effective enough. The new synthesis method makes the fabrication of the silica monolithic column (especially capillary column) much easier. All the structure parameters indicate that monolith PFA05 prepared by the above method is a good material for separation, with the merits of much higher surface area than usual commercial HPLC silica particles, suitable mesopore volume, narrow mesopore size distribution, low shrinkage and it is easily prepared.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3B
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• pp.472-486
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• 2000

This paper analysis the performance of joint receiving structure consisting of the decorrelating multiuser detection and beamfromenr-RAKE receive for DS-CDMA communication systems. In asynchronous transmission as the number of simultaneous users increase. the capacity of CDMA system becomes severly reduced due to the nonideal orthogonality between user-assigned PN sequences and improper power control. Accordingly, the CDMA receiving system becomes vulnerable to the multiple access interferences and the near-far problem under multipath fading channel environment. To withstand these undesired performance degradations, this paper proposes the new type of multiuser detection which has a form of the hybrid structure of concatenating beamformer-RAKE receiver and decorrelating multiuser detection. the beam former-RAKE receiver performs temporal and spatial diversity combining with alleviating fading effect and suppressing undesired interferences, and the multiuser detection plays a role of making the receiver robust to the near-far problem. Regarding the individual merit on the usage of either multiuser detection or beamformer-RAKE receiver, the hybrid one is expected to produce the enhanced performance in multipath fading CDMA channel. However major drawback of using decorrelating multiuser detection for practical deployment is arised from its computational complexity , which is exponentially increased as more number of users and transmitted symbols involve. To diminish the computational complexity, this paper exploits an efficient block Toeplitz inversion technique using matrix Levinson polynomial will be introduced. And this paper provided the mathematical analysis to show the efficiency of the proposed joint structure under the multipath propagation environment. And results of a series of exhaustive computer simulations are presented in order to demonstrate the overall performance of the proposed hybrid structure in multipath fading CDMA channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11C
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• pp.901-906
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• 2010

Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.

• Journal of Ocean Engineering and Technology
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• v.18 no.6 s.61
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• pp.79-83
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• 2004

The curved blocks which compose the bow and stem of a ship contain many skewed joints that are inclined horizontally and vertically. Most of these joints have a large fitness error and are continuously changing their form and are not easily accessible. The welding position and parameter values should be appropriately set in correspondence to the shape and the inclination of the joints. The welding parameters such as current, voltage, travel speed, and melting rate, are related to each other and their values must be in a specific limited range for the sound welding. These correlations and the ranges are dependent up on the kind and size of wire, shielding gas, joint shape and fitness. To determine these relationships, extensive welding experiments were performed. The experimental data were processed using several information processing technologies. The regression method was used to determine the relationship between current voltage, and deposition rate. When a joint is inclined, the weld bead should be confined to a the limited size, inorder to avoid undercut as well as overlap due to flowing down of molten metal by gravity. The dependency of the limited weld size which is defined as the critical deposited area on various factors such as the horizontally and vertically inclined angle of the joint, skewed angle of the joint, up or down welding direction and weaving was investigated through a number of welding experiments. On the basis of this result, an ANN system was developed to estimate the critical deposited area. The ANN system consists of a 4 layer structure and uses an error back propagation learning algorithm. The estimated values of the ANN were validated using experimental values.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.15-22
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• 2006

This paper presents a novel signal tracking algorithm for GNSS receivers using a MLE technique. In order to perform a robust signal tracking in severe signal environments, e.g., high dynamics for navigation vehicles or weak signals for indoor positioning, the MLE based signal tracking approach is adopted in the paper. With assuming white Gaussian additive noise, the cost function of MLE is expanded to the cost function of NLSE. Efficient and practical approach for Doppler frequency tracking by the MLE is derived based on the assumption of code-free signals, i.e., the cost function of the MLE for carrier Doppler tracking is used to derive a discriminator function to create error signals from incoming and reference signals. The use of the MLE method for carrier tracking makes it possible to generalize the MLE equation for arbitrary codes and modulation schemes. This is ideally suited for various GNSS signals with same structure of tracking module. This paper proposes two different types of MLE based tracking method, i.e., an iterative batch processing method and a non-iterative feed-forward processing method. The first method is derived without any limitation on time consumption, while the second method is proposed for a time limited case by using a 1st derivative of cost function, which is proportional to error signal from discriminators of conventional tracking methods. The second method can be implemented by a block diagram approach for tracking carrier phase, Doppler frequency and code phase with assuming no correlation of signal parameters. Finally, a state space form of FLL/PLL/DLL is adopted to the designed MLE based tracking algorithm for reducing noise on the estimated signal parameters.

• Journal of Pharmacopuncture
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• v.12 no.1
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• pp.67-76
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• 2009

Objective : Following central nervous system(CNS) injury, inhibitory influences at the site of axonal damage occur. Glial cells become reactive and form a glial scar, gliosis. Also myelin debris such as MAG inhibits axonal regeneration. Astrocyte-rich gliosis relates with up-regulation of GFAP and CD81, and eventually becomes physical and mechanical barrier to axonal regeneration. MAG is one of several endogenous axon regeneration inhibitors that limit recovery from CNS injury and disease. It was reported that molecules that block such inhibitors enhanced axon regeneration and functional recovery. Recently it was reported that treatment with anti-CD81 antibodies enhanced functional recovery in the rat with spinal cord injury. So in this current study, the author investigated the effect of the water extract of Uncariae Ramulus et Uncus on the regulation of CD81, GFAP and MAG that increase when gliosis occurs. Methods : MTT assay was performed to examine cell viability, and cell-based ELISA, western blot and PCR were used to detect the expression of CD81, GFAP and MAG. Then also immunohistochemistry was performed to confirm in vivo. Results : Water extract of Uncariae Ramulus et Uncus showed relatively high cell viability at the concentration of 0.05%, 0.1% and 0.5%. The expression of CD81, GFAP and MAG in astrocytes was decreased after the administration of Uncariae Ramulus et Uncus water extract. These results was confirmed in the brain sections following cortical stab injury by immunohistochemistry. Conclusion : The authors observed that Uncariae Ramulus et Uncus significantly down-regulates the expression of CD81, GFAP and MAG. These results suggest that Uncariae Ramulus et Uncus can be a candidate to regenerate CNS injury.

• Resources Recycling
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• v.26 no.1
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• pp.16-21
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• 2017

This paper relates to the synthesis of a source powder for SiC crystal growth. ${\beta}-SiC$ powders are synthesized at high temperatures (>$1400^{\circ}C$) by a reaction between silicon powder and carbon powder. The reaction is carried out in a graphite crucible operating in a vacuum ambient (or Ar gas) over a period of time sufficient to cause the Si+C mixture to react and form poly-crystalline SiC powder. End-product characterizations are pursued with X-ray diffraction analysis, SEM/EDS, particle size analyzer and ICP-OES. The purity of the end-product was analyzed with the Korean Standard KS L 1612.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.1
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• pp.16-28
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• 2014

This paper presents a novel high-power-factor circuit topology of AC to AC current-fed type high frequency resonant inverter which includes the function of power factor correction(PFC) in the proposed inverter to operate the AC input block with high power factor. The proposed circuit topology of AC to AC current fed type high resonant inverter removes DC link electrolytic capacitor and has also the one of power factor correction(PFC) in the inverter circuit without an additional PFC circuit since the input current by constituting it in parallel as an unit inverter, which assumes the class-E high frequency resonant inverter of conventional current-fed type, flows in the form of the resultant current flowing through each constant current reactor($L_{d1}$, $L_{d2}$). The circuit analysis of proposed inverter is generally described by adopting the normalized parameters and the evaluation of its operating characteristics are conducted by using the parameters such as the ratio of switching and resonant frequency(${\mu}$), coupling coefficient(k) and so on. An example of procedure for circuit design based on the characteristic values obtained from the theoretical analysis is presented. To confirm the validity of the theoretical analysis, the experimental results are also presented. In the future, the proposed inverter shows it can be practically used as power supply system for induction heating application, DC-DC converter etc.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.2
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• pp.206-212
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• 2006

Many image and video compression algorithms work by splitting the input image into blocks and producing variable-length coded bits for each block data. If variable-length coded data are transmitted consecutively, then the resulting coder is highly sensitive to channel errors. Therefore, most image and video techniques for providing some protection to the stream against channel errors usually involve adding a controlled amount of redundancy back into the stream. Such redundancy might take the form of resynchronization markers, which enable the decoder to restart the decoding process from the known state, in the event of transmission errors. The Error Resilient Entropy Code (EREC) is a well known method which can regain synchronization without any redundant information to convert from variable-length code to fixed-length code. This paper proposes an enhancement to EREC, which greatly improves its transmission ability for the compressed image quality without any redundant bits in the event of errors. The simulation result shows that the both objective and subjective quality of transmitted image is enhanced compared with the existing EREC at the same BER(Bit Error Rate).

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.145-149
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• 2011

Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.