• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.4 no.1
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• pp.65-75
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• 2006

Transparency on the Total System Performance Assessment (TSPA) is the key issue to enhance the public acceptance for a radioactive repository. To approve it, all performances on TSPA through Quality Assurance is necessary. The integrated Cyber R&D Platform is developed by KAERI using the T2R3 principles applicable for five major steps : planning, research work, documentation, and internal & external audits in R&D's. The proposed system is implemented in the web-based system so that all participants in TSPA are able to access the system. It is composed of three sub-systems; FEAS (FEp to Assessment through Scenario development) showing systematic approach from the FEPs to Assessment methods flow chart, PAID (Performance Assessment Input Databases) being designed to easily search and review field data for TSPA and QA system containing the administrative system for QA on five key steps in R&D's in addition to approval and disapproval processes, corrective actions, and permanent record keeping. All information being recorded in QA system through T2R3 principles is integrated into Cyber R&D Platform so that every data in the system can be checked whenever necessary. Throughout the next phase R&D, Cyber R&D Platform will be connected with the assessment tool for TSPA so that it will be expected to search the whole information in one unified system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.2
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• pp.627-633
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• 2020

Assembly process data can be gathered in real time in a manufacturing execution system (MES) server using proximity sensors, barcodes, RFID, ZigBee, Bluetooth, wireless sensor networks, etc. Although this is suitable for identifying process flow and checking production progress, it is difficult to trace the location of individual workers in real time for missing work or trajectories within the work area. To overcome this, the location and trajectory of the working tool can be analyzed in real time through a position tracking system of an operator's working tool. It can instruct the operator to perform a consistent working process. Productivity and quality improvement can be achieved by an alarming or blocking operator with possible assembly defects during the assembly process in real time. To this end, we developed a real-time tool position-tracking sensor system based on Ultra Wide Band (UWB) trilateration using a Kalman filter to eliminate mechanical vibration and radio communication noise.

• The Journal of the Korea Contents Association
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• v.11 no.12
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• pp.931-942
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• 2011

As the social infrastructure becomes deteriorated, its maintenance cost has been increased rapidly. There are growing needs to manage facilities systematically to reduce this kind of maintenance budget, and furthermore to avoid safety accidents in Korea. Asset management is widely used in New Zealand, the United States, Great Britain to manage their social facilities. In these countries, standardized information model and its system are developed and in service for asset management. There are several researches on asset management of social infrastructure in Korea, and the KTAM-40 work procedure is one of the main results for these researches. In this paper, the IIMM of New Zealand and the KTAM-40 of Korea, were surveyed to develop a business architecture of the highway asset management system. A new business architecture for the highway asset management system is proposed based on the KTAM-40 work procedure: First, the organization and its role for the highway asset management are defined. Second, business functions of the highway asset management are classified. Third, the highway asset management functions and the flow of information are defined. In the last section, differences between the newly designed architecture and the other systems' architecture is reviewed.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.3
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• pp.266-277
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• 2003

Every conceptual temporal rat relationship can be described using one of seven relations (before, meets, overlaps, during, starts, finishes, and equals ). The conceptual representation provides an efficient means for our multimedia authoring system to automatically fill in the necessary timing details. We developed a multimedia Presentation authoring system that supports a mechanism for conceptually representing the temporal relations of different media. Among the many editors that make up our system, the temporal relation editor provides users with an intuitive mechanism for representing the conceptual flow of a presentation by simple and direct graphical manipulations. Our system is based on the SMIL(Synchronized Multimedia Integration Language). The conceptual temporal relation editor and other editors of our system exchange their information in real-time and automatically generate SMIL codes through the SMIL Object Manager. Our system uses TRN(Temporal Relation Network) as its internal multimedia presentation representation. The TRN corresponds exactly to the structure seen in the graphical representation of the presentation. A parallel relationship found in a TRN can be collapsed into a single synchronization block. This facilitates the determination of the playing time of each component and can be the basic unit for reusability of already prepared blocks of presentation code.

• Cartoon and Animation Studies
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• s.47
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• pp.273-294
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• 2017

Korea has suffered numerous casualties due to a lot of accidents caused by safety insufficiency in recent years. Therefore, safety education is more important than ever before, and 'how to educate with what contents' is an important subject. Especially, experience education is effective rather than theoretical education because of the nature of safety education. However, it is not easy to design and develop these safety education programs. There is not much opportunity to access first-aid training, which is a part of safety education, unless it is compulsory to learn through public institutions. As a result, program utilization on safety education in Korea is still insufficient to what it should be. With that taken into account, this study proposed an effective serious game with fun and immersion for medical first-aid education. To do this, we analyzed five medical games through 20 cases of first-aid applications and elicited five factors that enhance the usability of serious games. With an analysis of five medical games, we selected one game to borrow the game rules, and applied the elicited five elements in the forms of level-up structure, iterative learning, compensation outcomes, competition system, and information transfer. The proposed medical education functional games should have 1) a character that plays a role of a patient, 2) a narrative flow that shows the situation, 3) the user should judge the situation and induce first aid. 4) compensation, levels, and simple repetition should be designed, and 5) information should be shared with the others in the given community. The results of this study is believed to contribute to enhance the medical emergency education in Korea.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11B
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• pp.920-929
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• 2004

Nowadays, wireless packet data services are provided over cdma2000 1x/1xEV-DO mobile communication network and Portable Internet are being standardized for users demanding higher data rate services. Portable Internet can provide high data rate services, but its service coverage is relatively small. If Portable Internet may be integrated with cdma2000 mobile networks, users are able to choose the best service according to service areas and get seamless services while they are moving around. At the same time, it is cost-effective for operators to construct and maintain the integrated network. For the purpose of effectively integrating Portable Internet into cdma2000 networks, we propose an integration scheme including network architecture, protocol architecture, functions in network elements, interfaces between them, and call-flow procedures. The integration scheme proposed in this paper adopts a tightly-coupled architecture for unified authentication/accounting and seamless services. In addition, the scheme can be implemented without modifying the existing cdma2000 mobile communication networks. It is also simple to develop the dual-mode mobile station. Through the simulation results based on the performance model for handoffs between cdma2000 and Portable Internet, it has teen validated that the proposed scheme diminishes packet losses compared with the loosely-coupled architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9B
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• pp.751-759
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• 2008

Carrier Ethernet backbone network integrates distributed layer-2 based metro networks. In this networks, Multiple Spanning Tree Protocol (MSTP) has been uscd as a main routing protocol that allows multiple spanning trees in a network. A better routing protocol called IEEE802.1aq - Shortest Path Bridging (SPB) is recently proposed, that generates the shortest spanning tree per a destination node. As SPB provides a routing path per a destination node, there is no way to adapt network traffic at normal condition. If we are free from the principle of "a spanning tree per a destination node", we can achieve adaptive routing. Based on this philosophy, we propose a new spanning tree based protocol - Edge Node Divided Spanning Tree (ENDIST). ENDIST divides an edge node into sub-nodes as many as connecting links from the node and each sub-node generates a single shortest path tree based on SPB. Depending on network or nodal status, ENDIST chooses a better routing path by flow-basis. This added traffic engineering ability contributes to enhanced throughput and reduced delay in backbone networks. The simulation informs us that ENDIST's throughput under heavy load performs about 3.4-5.8 and 1.5-2.0 times compared with STP's and SPB's one respectively. Also, we verified that ENDIST's throughput corresponds to the theoretical upper bound at half of cases we investigated. This means that the proposed ENDIST is a dramatically enhanced and the close-to-perfect spanning tree based routing schemes.

• Journal of Korean Society of Transportation
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• v.31 no.4
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• pp.32-46
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• 2013

Because of short length between interchanges, traffic congestion has been caused by a lot of short trip traffic in the urban section of interregional expressway. Also, in case of expressway with Bus Only Lane, bus causes dangerous situation by conflicting between vehicles and buses in order to access from Bus Only Lane to IC. Therefore, this study aims to propose Express Lane applied by Bus Only Lane as a new lane operation in order to efficiently operate and to analyze the effectiveness on constructing Express Lane to the Pangyo-Hannam section in Gyeongbu Expressway. The study analyzes effectiveness by scenario using the micro traffic simulation tool, VISSIM 5.4. For this, the indicators which evaluate construction effect of Express Lane, are used by average delay time, average speed and total travel time. The results of the study showed the best effectiveness when Express Lane installed one, and it represented an ideal traffic condition when long distance trip traffic of the whole traffic is 25% in the study section. Therefore, the construction of Express Lane using Bus Only Lane achieves positive effectiveness on safety and expense aspect as well as uncongested flow.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.185-197
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• 2001

Recently, the design method by VHDL coding and synthesis has been used widely. As the integration ratio increases, the amount design by VHDL at a time also increases so many coding errors occur in a design. Thus, lots of time and effort is dissipated to detect those coding errors. This paper proposed a method to verify the coding errors in VHDL behavioral-level designs. As the methodology, we chose the method to detect the coding error by applying the generated set of verifying patterns and comparing the responses from the error-free case(gold unit) and the real design. Thus, we proposed an algorithm to generate the verifying pattern set for the coding errors. Verifying pattern generation is peformed for each code and the coding errors are classified as two kind: condition errors and assignment errors. To generate the patterns, VHDL design is first converted into the corresponding CDFG(Control & Data Flow Graph) and the necessary information is extracted by searching the paths in CDFG. Path searching method consists of forward searching and backward searching from the site where it is assumed that coding error occurred. The proposed algorithm was implemented with C-language. We have applied the proposed algorithm to several example VHDL behavioral-level designs. From the results, all the patterns for all the considered coding errors in each design could be generated and all the coding errors were detectable. For the time to generate the verifying patterns, all the considered designed took less than 1 ［sec］ of CPU time in Pentium-II 400MHz environments. Consequently, the verification method proposed in this paper is expected to reduce the time and effort to verify the VHDL behavioral-level designs very much.