• Speech Sciences
• /
• v.3
• /
• pp.177-186
• /
• 1998

This paper describes the procedure of implementing a real-time speech codec, G.723.1 which was developed by DSP Group and standardized by ITU-T, using fixed-point DSP, ADSP-2181. This codec has two bit rates associated with it, 5.3 and 6.3 kbit/s. We implemented only one bit rate, 6.3 kbit/s, of the two with fixed-point 32-bit precision. According to the result of the experiment, the amount of computational burden is about 55 MIPS and its quality is similar to the result of the PC simulation with floating-point arithmetic. In this paper, we proposed a method to use a fixed-point DSP and a procedure for developing a real-time speech codec using DSPs and finally developed a G.723.l speech codec for ADSP-2181.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.4 no.3
• /
• pp.325-335
• /
• 1994

The spinel $MgO.Al_20_3$ single crystals were grown by FZ (floating zone) method. Its melting point is about, $2135^{\circ}C$ and is important to the process of the growth from the melt. There have been some reports of the growth by Czochralski and Verneuil method. However, this study is the first trial to the spinel crystal with the application of FZ method. In this study, $MgAl_2O_4$ spinel crystals were grown by using FZ method which uses the ellipsoidal mirror furnace having infrared halogen lamps as a heat source. With dopants of transition metal ions, it was possible to melt the feed rod which does not absorb the infrared rays due to the transparent properties to infrared ray of spinel itself and the red, green and blue colored spinel single crystals could be grown more easily. As a conclusion, the purpose of this study is to find the spinel single crystal growth mechanism with respect to th growth interfaces and molten zone stability and to characterize the state of growth resulting from the concavity to the melt of interfaces.

• Journal of the Computational Structural Engineering Institute of Korea
• /
• v.31 no.5
• /
• pp.215-226
• /
• 2018

In this paper, to estimate the dynamic behavior of a submerged floating tunnel(SFT) by underwater explosion(UE), the SFT is modeled and analyzed by the explicit structural analysis package LS-DYNA. The section of SFT near to explosion point is modeled to shell and solid elements using elasto-plasticity material model for concrete tubular section and steel lining. And the other parts of the SFT are modeled to elastic beam elements. Also, mooring lines are modeled as tension-only cable elements. Total mass of SFT is including an added mass by hydrodynamic effect. The buoyancy on the SFT is considered in its initial condition using a dynamic relaxation method. The accuracy and the feasibility of the analysis model aree verified by the results of series of free field analysis for UE. And buoyancy ratio(B/W) of SFT, the distance between SFT and an explosion point and the arrangement of mooring line aree considered as main parameters of the explosion analysis. As results of the explosion analysis, the dynamic responses such as the dent deformation by the shock pressure are responded less as more distance between SFT and an explosion point. However, the mooring angle of the diagonal mooring system can not affect the responses such as the horizontal displacement of SFT by the shock pressure.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.1153-1156
• /
• 1998

We describe a design of a simple but efficient floatingpoint processing architecture expoiting concurrent execution of scalar instructions for high performance in general-purpose microprocessors. This architecture employs 3 stage pipeline asyncronously working with integer processing unit to regulate instruction flows between two arithmetic units.

• Magazine of the Korean Society of Agricultural Engineers
• /
• v.29 no.2
• /
• pp.23-29
• /
• 1987

This study was fulfilled by the floating lysimeter method at the experimental farm of Kon-Kuk University from August to November of 1986 to investigate the amount of evapotranspiration by the growing periods, evapotranspiration ratio, amount of watering per one time, days of intermission, soil moisture extraction pattern and crop coefficient of the Chinese cabbage cultivated in the sandy loam soil at the watering point of pF2.O. The results obtained are summarized as follows: 1.The total evapotranspiration during the growing period was 267.2mm, which was 3. 99mm by daily average, and the maximum evapotranspiration showed in the mid ten days of September with the value of 5.81mm I day. 2.The evapotranspiration ratio by the growing stages increased from the last ten days of September and showed maximum in the beginning of October, and the average evapotranspiration ratio was 1.4. 3.The days of watering intermission at the watering point of pF2.O was 2.4 days, and the average yield per plant was 3,228 g. 4. The soil moisture extraction pattern in the initial stage was 78.9 % in the 1st and 2nd soil layer and 21.1 % in the 3rd and 4th layer, and the mid-season stage, the moisture extraction proportion of the under layer accounted for 38.8 % which showed that the root elongated to the lowest soil layer. 5.The average crop coefficient(Kc) of the tested crop during the growing period was 0.67 by Penman equation and 2.36 by Pan Evaporation equation, which showed high difference by the calculation methods, and the changes of crop coefficient by the growing stages by Penman equation was favorable than those calculated by other met-hods.

• Smart Structures and Systems
• /
• v.14 no.6
• /
• pp.1131-1150
• /
• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• Coupled systems mechanics
• /
• v.2 no.4
• /
• pp.389-410
• /
• 2013

Three-dimensional Lagrangian fluid finite element is applied to seismic response analysis of an oil storage tank with a floating roof. The fluid element utilized in the present analysis is formulated based on the displacement finite element method considering only volumetric elasticity and its element stiffness matrix is derived by using one-point integration method in order to avoid volumetric locking. The method usually adds a rotational penalty stiffness to satisfy the irrotational condition for fluid motion and modifies element mass matrices through the projected mass method to suppress spurious hourglass-mode appeared in compensation for one-point integration. In the fluid element utilized in the present paper, a small hourglass stiffness is employed. The fluid and structure domains for the objective oil storage tank are modeled by eight-node solid elements and four-node shell elements, respectively, and the transient response of the floating roof structure or the free surface are evaluated by implicit direct time integration method. The results of seismic response analyses are compared with those by other method and the validation of the present analysis using three-dimensional Lagrangian fluid finite elements is shown.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.3
• /
• pp.517-524
• /
• 2001

This paper describes a design of radix-2 SRT divider unit, which supports IEEE-754 floating-point standard, using redundant binary number system (RBNS). With the RBNS, the partial quotient decision logic can operate about 20-% faster, as well as can be implemented with a simple hardware when compared to the conventional methods based on two's complement arithmetic. By using a new redundant binary adder proposed in this paper, the mantissa divider is efficiently implemented, thus resulting in about 20% smaller area than other works. The divider unit supports double precision format, five exceptions and four rounding modes. It was verified with Verilog HDL and Verilog-XL.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.12
• /
• pp.723-731
• /
• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.365-368
• /
• 2001

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.