• Journal of the Korea Society of Computer and Information
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• v.20 no.12
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• pp.1-8
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• 2015

Wear leveling techniques have been studied to prolong the lifetime of NAND flash memory. Most of studies have used Program/Erase(P/E) cycles as wear index for wear leveling. Unfortunately, P/E cycles could not predict the real lifetime of NAND flash blocks. Therefore, these algorithms have the limited performance from prolonging the lifetime when applied to the SSD. In order to apply the real lifetime, wear leveling algorithms, which use raw Bit Error Rate(rBER) as wear index, have been studied in recent years. In this paper, we propose CrEWL(Cold data identification using raw Bit error rate in Wear Leveling), which uses rBER as wear index to apply to the real lifetime. The proposed wear leveling reduces an overhead of garbage collections by using HBSQ(Hot Block Sequence Queue) which identifies hot data. In order to reduce overhead of wear leveling, CrEWL does not perform wear leveling until rBER of the some blocks reaches a threshold value. We evaluate CrEWL in comparison with the previous studies under the traces having the different Hot/Cold rate, and the experimental results show that our wear leveling technique can reduce the overhead up to 41% and prolong the lifetime up to 72% compared with previous wear leveling techniques.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.63-69
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• 2019

Recently, ultra-low latency flash storage devices such as Z-SSD and Optane SSD were introduced with the significant technological improvement in the storage devices which provide much faster response time than today's other NVMe SSDs. With such ultra-low latency, $10{\mu}s$, storage devices the cost of context switch could be an overhead during interrupt-driven I/O completion process. As an interrupt-driven I/O completion process could bring an interrupt handling overhead, polling or hybrid-polling for the I/O completion is known to perform better. In this paper, we analyze tail latency problem in a polling process caused by process scheduling in data center environment where multiple applications run simultaneously under one system and we introduce our adaptive polling selection technique which dynamically selects efficient processing method between two techniques according to the system's conditions.

• Annual Conference of KIPS
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• 2009.04a
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• pp.647-650
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• 2009

IPTV(Internet Protocol Television)는 차별화된 초고속 광대역 네트워크를 기반으로 기존 TV의 단점을 보완하여 차세대 DTV 시장을 주도할 것으로 예상된다. IPTV의 저장용량이 증가하는 추세에 따라 SSD(Solid State Disk)가 NAND 플래시 메모리를 대체 할 것으로 예상된다. 본 논문에서는 IPTV의 저장장치인 SSD의 수명을 증가시키고 플래시메모리의 특성인 마모도 제한을 고려하지 않은 지움 정책(Garbage-Collection)을 사용하는 YAFFS(Yet Another Flash FileSystem)의 문제점을 해결하기 위해 블록을 내용기반 리스트로 관리하고 블록스왑을 사용하는 내용기반 지움 정책을 제안한다. 기존 파일시스템 보다 수명을 향상 시키는 내용기반 파일시스템을 설계 및 구현하여 성능을 분석하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.7
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• pp.425-432
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• 2014

This paper proposes a wear-leveling algorithm that exploits the properties of SSD memories with multi-channel and multi-way architecture. When a write request arrives, the proposed algorithm classifies the stored data in DRAM buffer into hot or cold according to logical address access frequency, and performs data allocation to reduce deviation of block erase counts. It lowers the chance of increasing erase count by allocating cold data to blocks which have high erase count. Effectiveness of the proposed algorithm is verified by executing various applications on a multi-channel, multi-way SSD simulator. Experimental results show that differences in erase count among blocks is reduced by an average of 9.3%, and total erase count decreases by 4.6%, when compared to previous wear-leveling algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.539-545
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• 2015

Deduplication technique can expand the lifespan and capacity of flash memory-based storage devices by eliminating duplicated write operations. The deduplication techniques can be classified into two approaches, i.e., online and offline approaches. We propose an offline deduplication technique that uses a lightweight hash algorithm, whereas the previous offline technique uses a high-cost hash algorithm. Therefore, the memory space for caching hash values can be reduced, and more pages can be examined for deduplication during short idle intervals. As a result, it can provide shorter write latencies compared to the online approach, and can show low garbage collection costs compared to the previous offline deduplication technique.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.357-359
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• 2018

최근 메모리 반도체 시장은 SD(Secure Digital) 메모리 카드, SSD(Solid State Drive)등의 보급률 증가로 메모리 반도체의 시장이 대규모로 증가하고 있다. 메모리 반도체는 개인용 컴퓨터 뿐만 아니라 스마프폰, 테플릿 PC, 교육용 임베디드 보드 등 다양한 산업에서 이용 되고 있다. 또한 메모리 반도체 생산 업체가 대규모로 메모리 반도체 산업에 투자하면서 메모리 반도체 시장은 대규모로 성장되었다. 플래시 메모리는 크게 NAND-Type과 NOR-Type으로 나뉘며 플로팅 게이트 셀의 전압의 따라 SLC(Single Level Cell)과 MLC(Multi Level Cell) 그리고 TLC(Triple Level Cell)로 구분 된다. SLC 및 MLC NAND-Type 플래시 메모리는 많은 연구가 진행되고 이용되고 있지만, TLC NAND-Tpye 플래시 메모리는 많은 연구가 진행되고 있지 않다. 본 논문에서는 기존에 제안된 SLC 및 MLC NAND-Type 플래시 메모리에서 제안된 큐브 패턴을 TLC NAND-Type 플래시 메모리에서 적용 가능한 큐브 패턴 및 알고리즘을 제안한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.291-302
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• 2013

NAND flash memory (NFM) based storage devices, e.g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solutions when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research shows that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e.g. request length, update ratios, read-and-modify ratios. Experimental results show that the optimized page and block size can achieve up to 15 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM.

• Journal of Advanced Navigation Technology
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• v.20 no.4
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• pp.321-328
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• 2016

Typical MLC NAND flash devices are considered less reliable than SLC NAND flash devices. Although raw bit error rate (RBER) of MLC flash had been considered approximately 1000times or more higher than that of SLC flash, recent research conducted on Google's data center shows that it is much lower than such expectation. Based on the research, we devised In Drive Data Duplication (IDDD) scheme that efficiently exploit MLC flash's sufficient capacity to improve its data reliability without structural complexity increment using SSD intrinsic firmware layer, and showed the data reliability expectation of MLC flash could be significantly higher than that of SLC flash from measured and calculated error rates. Even though RBER of SLC flash was lower than that of MLC flash in 44 out of 48 cases we studied, applying IDDD scheme, RBER of MLC flash was became lower than that of SLC in all 48 cases and uncorrectable bit error rate (UBER) of MLC flash was became lower than that of SLC flash in 45 out of 48 cases.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.54-62
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• 2015

Although NAND flash-based SSD (Solid-State Drive) provides superior performance in comparison to HDD (Hard Disk Drive), it has a major drawback in write endurance. As a result, the lifetime of SSD is determined by the workload and thus it becomes a big challenge in current technology trend of such as the shifting from SLC (Single Level Cell) to MLC (Multi Level cell) and even TLC (Triple Level Cell). Most previous studies have dealt with wear-leveling or improving SSD lifetime regarding hardware architecture. In this paper, we propose the optimal configuration of host I/O stack focusing on file system, I/O scheduler, and link power management using JEDEC enterprise workloads in terms of WAF (Write Amplification Factor) which represents the efficiency perspective of SSD life time especially for host write processing into flash memory. Experimental analysis shows that the optimum configuration of I/O stack for the perspective of SSD lifetime is MinPower-Dead-XFS which prolongs the lifetime of SSD approximately 2.6 times in comparison with MaxPower-Cfq-Ext4, the best performance combination. Though the performance was reduced by 13%, this contributions demonstrates a considerable aspect of SSD lifetime in relation to I/O stack optimization.

• Smart Media Journal
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• v.4 no.2
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• pp.62-67
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• 2015

During several decades, hard disk drive(HDD) has been used in most computer systems as secondary storage and, however, the performance enhancement of HDD is limited by its mechanical properties. On the other hand, although the flash memory based solid state drive (SSD) has more advantages over HDD such as high performance and low noise, SSD is still too expensive for common usage and expected to take several years to replace HDD completely. Therefore, SSD caching mechanism using the SSD as a cache of high capacity HDD has been highlighted lately. The representatives of SSD caching mechanisms are typically bcache, dm-cache, Flashcache, and EnhanceIO. Each of them has its own internal mechanism and implementation, and this makes them to show their own pros. and cons. In this paper, we analyze the characteristics of each SSD caching mechanisms and compare the performance of them under various workloads. We expect that our contribution will be useful to enhance the performance of SSD caching mechanisms.