• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.62-68
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• 2007

This paper proposes an efficient integer division algorithm for high speed FPGAs' which support built-in RAMs' and multipliers. The integer division algorithm is iterative with RAM-based LUT and multipliers, which minimizes the usage of logic fabric and connection resources. Compared with some popular division algorithms such as division by subtraction or division by multiply-subtraction, the number of iteration is much smaller, so that very low latency can be achieved with pipelined implementations. We have implemented our algorithm in the Xilinx virtex-4 FPGA with VHDL coding and have achieved 300MSPS data rate in 17bit integer division. The algorithm used less than 1/6 of logic slices, 1/4 of the built-in multiply-accumulation units, and 1/3 of the latencies compared with other popular algorithms.

• Journal of IKEEE
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• v.27 no.4
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• pp.601-609
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• 2023

In this paper, we propose an artificial intelligence-based high-speed fault diagnosis method using an FPGA in the event of a ground fault in a DC system. When applying artificial intelligence algorithms to fault diagnosis, a substantial amount of computation and real-time data processing are required. By employing an FPGA with AI-based high-speed fault diagnosis, the DC breaker can operate more rapidly, thereby reducing the breaking capacity of the DC breaker. therefore, in this paper, an intelligent high-speed diagnosis algorithm was implemented by collecting fault data through fault simulation of a DC system using Matlab/Simulink. Subsequently, the proposed intelligent high-speed fault diagnosis algorithm was applied to the FPGA, and performance verification was conducted.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1565-1567
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• 2004

Various defects are found in FPD (Flat Panel Display) manufacturing process. So detecting these defects early and reprocessing them is an important factor that reduces the cost of production. In this paper, the bare glass inspection system for the FPD which is the early process inspection system in the FPD manufacturing process is designed and implemented using the high performance and accuracy CCD line scan camera. For the preprocessing of the high speed line image data, the Image Processing Part (IPP) is designed and implemented using high performance DSP (Digital signal Processor), FIFO (First in First out), FPGA (Field Programmable Gate Array) and the Data Management and System Control part are implemented using ARM (Advanced RISC Machine) processor to control many IPP and cameras and to provide remote users with processed data. For evaluating implemented system, experiment environment which has an area camera for reviewing and moving shelf is made.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.998-1004
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• 2008

In this paper, a visual servoing control technique of humanoid robot arms is implemented for tracking a moving object. An embedded time-delayed controller is designed on an FPGA(Programmable field gate array) chip and implemented to control humanoid robot arms. The position of the moving object is detected by a stereo vision camera and converted to joint commands through the inverse kinematics. Then the robot arm performs visual servoing control to track a moving object in real time fashion. Experimental studies are conducted and results demonstrate the feasibility of the visual feedback control method for a moving object tracking task by the humanoid robot arms called the ROBOKER.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.5
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• pp.684-696
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• 2018

The mission in missile systems can be conducted with multiple phases according to the characteristics of the systems and the targets. The safeguarded multi-phase mission includes a safeguarded phase before launch for considering the safety of operators in unexpected squib activation. However, the safeguard function should be disabled after launch to complete the mission. Therefore, the squib system needs to be selectively activated according to the phases. This paper presents a selective squib activation and check circuit design for safeguarded multi-phase missions in missile systems. The presented circuit design was implemented with various electronic components including a field-programmable gate array(FPGA). Its functions and performance were validated by both many ground tests and several flight tests.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.146-148
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• 2008

본 논문에서는 계통의 전력품질을 향상시키기 위해 사용되어지는 전류제어형 전압원 인버터를 구동하기 위한 PRT(Polarized RamTime) 전류제어알고리즘의 구현방법을 설명한다. PRT 전류제어알고리즘은 스위칭 시퀀스의 예측이 가능하고 히스테리시스 전류제어기법의 단점인 가변스위칭 주파수 문제를 해결할 수 있다. 본 연구에서는 전류제어형 전압원인버터용 PRT 전류제어알고리즘을 FPGA(Field Programmable Gate Array)를 이용하여 구현하였고, 이의 유용성을 확인하기 위해 1KVA급 계통연계 전류제어형 전압원 인버터에 적용하여 실험 하였다.

• International Journal of Aeronautical and Space Sciences
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• v.13 no.2
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• pp.260-265
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• 2012

Satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2). Based on the mission requirements of STSAT-2, the conventional analog-type sun sensors were found to be inadequate, motivating the development of a compact, fast and fine digital sun sensor (FDSS). The FDSS uses a CMOS image sensor and has an accuracy of less than 0.03degrees, an update rate of 5Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize its weight. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA), which acquires images from the CMOS sensor, and stores and processes the image data. The sensor accuracy is maintained by a rigorous centroid algorithm. This paper describes the FDSS designs, realizations, tests and calibration results.

• ETRI Journal
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• v.33 no.1
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• pp.71-77
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• 2011

Up to 10% of the global population suffers from color vision deficiency (CVD) [1], especially deuteranomaly and protanomaly, the conditions in which it is difficult to discriminate between red and green hues. For those who suffer from CVD, their career fields are restricted, and their childhood education is frustrating. There are many optical eye glasses on the market to compensate for this disability. However, although they are attractive due to their light weight, wearing these glasses will decrease visual brightness and cause problems at night. Therefore, this paper presents a supplementary device that comprises a head-mounted display and an image sensor. With the aid of the image processing technique of digital color space adjustment implemented in a high-speed field-programmable gate array device, the users can enjoy enhanced vision through the display without any decrease in brightness.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1682-1691
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• 2015

In this paper, a real time implementation of selective harmonic elimination pulse width modulation (SHEPWM) using Real Coded Genetic Algorithm (RGA), Particle Swarm Optimization technique (PSO) and a new technique known as Linearization Method (LM) for Single Phase Matrix Converter (SPMC) is designed and discussed. In the proposed technique, the switching frequency is fixed and the optimum switching angles are obtained using simple mathematical calculations. A MATLAB simulation was carried out, and FFT analysis of the simulated output voltage waveform confirms the effectiveness of the proposed method. An experimental setup was also developed, and the switching angles and firing pulses are generated using Field Programmable Gate Array (FPGA) processor. The proposed method proves that it is much applicable in the industrial applications by virtue of its suitability in real time applications.