• Speech Sciences
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• v.11 no.2
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• pp.211-216
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• 2004

In this paper, we present a fast encoding algorithm for vector quantization with an approximate Euclidean distance calculation. An approximation is performed by converting floating point to the near integer. An inequality between the approximate Euclidean distance and the nearest distance is developed to avoid unnecessary distance calculations. Since the proposed algorithm rejects those codewords that are impossible to be the nearest codeword, it produces the same output as conventional full search algorithm.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.3
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• pp.71-79
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• 1998

This paper introduces a new optimization algorithm which is combined with genetic algorithm and random tabu search method. Genetic algorithm is a random search algorithm which can find the global optimum without converging local optimum. And tabu search method is a very fast search method in convergent speed. The optimizing ability and convergent characteristics of a new combined optimization algorithm is identified by using a test function which have many local optimums and an optimum allocation of pipe support. The caculation results are compared with the existing genetic algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1392-1400
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• 1999

In this paper, we propose a two-stage fast full search algorithm for block motion estimation that produces the same performance to that of full search algorithm (FSA) but with remarkable computation reduction. The proposed algorithm uses the search region subsampling and the difference of adjacent pixels in the current block. In the first stage, we subsample the search region by a factor of 9, and then calculate mean absolute error (MAE) at the subsampled search points. And in the second stage, we reduce the search points that need block matching process by using the lower bound of MAE value at each search Point. We Set the lower bound of MAE value for each search point from the MAE values which are calculated at the first stage and the difference of adjacent pixels in the current block. The experimental results show that we can reduce the computational complexity considerably without any degradation of picture quality.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1231-1238
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• 2005

This paper presents a new fast encoding algorithm for image vector quantization that incorporates the partial distances of multiple features with a multidimensional look-up table (LUT). Although the methods which were proposed earlier use the multiple features, they handles the multiple features step by step in terms of searching order and calculating process. On the other hand, the proposed algorithm utilizes these features simultaneously with the LUT. This paper completely describes how to build the LUT with considering the boundary effect for feasible memory cost and how to terminate the current search by utilizing partial distances of the LUT Simulation results confirm the effectiveness of the proposed algorithm. When the codebook size is 256, the computational complexity of the proposed algorithm can be reduced by up to the $70\%$ of the operations required by the recently proposed alternatives such as the ordered Hadamard transform partial distance search (OHTPDS), the modified $L_2-norm$ pyramid ($M-L_2NP$), etc. With feasible preprocessing time and memory cost, the proposed algorithm reduces the computational complexity to below the $2.2\%$ of those required for the exhaustive full search (EFS) algorithm while preserving the same encoding quality as that of the EFS algorithm.

• Journal of the Korea Computer Industry Society
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• v.4 no.12
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• pp.1043-1052
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• 2003

In this paper, we present a fast motion estimation algorithm to reduce the computations of block matching algorithm for motion estimation in video coding. The proposed algorithm is based on Multi-level Successive Elimination Algorithm and Efficient Multi-level Successive Elimination Algorithms. The best estimate of the motion vectors can be obtained by hierarchical search point sampling and thus the proposed algorithm can decrease the number of matching evaluations that require very intensive computations. The efficiency of the proposed algorithm was verified by experimental results.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.86-94
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• 1998

This paper proposes a new fast block-matching algorithm, named MFSS(Modified Four-Step Search) algorithm, which has better performance and is more adequate for hardware realization than the existing fast algorithms. The proposed algorithm is suitable for hardware realization since it has a unique regularity during the search procedure. It is shown from simulation results that its performance is close to that of FS(Full Search) algorithm. This paper also proposes a VLSI architecture and presents some design results of a motion estimator and compensator which adopted the MFSS algorithm. The important aspects considered in designing a motion estimator and compensator are hardware complexity of design results, and total delay needed to generate the motion compensated data after finding the motion vectors. Hardware complexity is minimized by using just nine PE(Process Element)'s, and total delay is minimized by sharing search memory of the motion estimator and compensator.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2S
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• pp.638-648
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• 2000

This paper introduces a new technique for block is matching motion estimation. Since the temporal correlation of the image sequence, the motion vector of a block is highly related to the motion vector of the same coordinate block in the previous image frame. If we can obtain useful and enough information from the motion vector of the same coordinate block of the previous frame, the total number of search points used to find the motion vector of the current block may be reduced significantly. Using that idea, an efficient predicted direction search algorithm (PDSA) for block matching algorithm is proposed. Based on the direction of the blocks of the two successive previous frames, if the direction of the to successive blocks is same, the first search point of the proposed PDSA is moved two pixels to the direction of the block. The searching process after moving the first search point is processed according to the fixed search patterns. Otherwise, full search is performed with search area $\pm$2. Simulation results show that PSNR values are improved up to the 3.4dB as depend on the image sequences and improved about 1.5dB on an average. Search times are reduced about 20% than the other fast search algorithms. Simulation results also show that the performance of the PDSA scheme gives better subjective picture quality than the other fast search algorithms and is closer to that of the FS(Full Search) algorithm.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.2
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• pp.20-28
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• 2003

Recently we need a faster and more accurate motion vector search algorithm for ASIC(Application Specific IC) or small systems. Block motion estimation using Full Search(FS) algorithm provides the best visual quality and PSNR, but it requires intensive computations. The previously proposed fast algorithms reduced the number of computations by limiting the number of searching locations. This is accomplished at the expense of less accuracy of motion estimation and gives rise to an appreciably higher SAD(Sum of Absolute Difference) for motion compensated images. In this paper we exploit the spatial correlation of motion vectors and present a fast motion estimation scheme which uses the predicted motion vector(PMV). The PMV scheme is more clear and simpler than the previously proposed algorithms which also use adjacent motion vectors. Simulation results with standard video sequences show that the PMV scheme is faster and more accurate than other algorithms such as Nearest-Neighbors Search(NNS) algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.167-174
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• 2000

The three-step search(TSS) algorithm, a simple and gradual motion estimation algorithm, has been widely used in some low bit-rate video compression. We propose a new fast block motion estimation algorithm using the characteristics of motion in search region. Most of motion vectors exist in the center region of search area, so the notion in that region is examined more closely than TSS in this paper. Also in a search step, motion vector is estimated in the local area which is not overlapped with the search area in previous step, considering the all possible direction of motion. Therefore, we get the better motion estimation and reduce computational time in compared with the conventional methods.